I2C Clock Register (I2C1_Ckcfgr) - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual

13.11.8 I2C Clock register (I2C1_CKCFGR)

Offset address: 0x1C
15 14 13 12
F/S DUTY Reserved
Bit Name
15 F/S
14 DUTY
[13:12] Reserved
[11:0] CCR
V1.3
11 10 9 8
Access
Master mode selection bit.
RW 1：Fm mode I2C.
0：Sm mode I2C
Duty cycle of high-level time over low-level time
in Fm.
RW
1：36%；
RO Reserved
RW Clock control register in Fm/Sm mode
7 6 5
CCR[11:0]
Description
0：33.3%。
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4 3 2 1
Reset value
0
0
0
0
0