Tim1-Related Registers List; Timer Synchronization Mode; Control Register 1 (Tim1_Ctlr1) - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual

10.3.10 Timer synchronization mode

Timers are capable of outputting clock pulses (TRGO) and receiving inputs from other timers (ITRx). The
source of ITRx (TRGO from other timers) is different for different timers. The timer internal trigger
connections are shown in Table 10-2.
From timer
TIM1
TIM2
10.3.11 Debug mode
When the system enters debug mode, the timer continues to run or stops according to the settings of the DBG
module.
10.4 Register description
Name
R16_TIM1_CTLR1
R16_TIM1_CTLR2
R16_TIM1_SMCFGR
R16_TIM1_DMAINTENR
R16_TIM1_INTFR
R16_TIM1_SWEVGR
R16_TIM1_CHCTLR1
R16_TIM1_CHCTLR2
R16_TIM1_CCER
R16_TIM1_CNT
R16_TIM1_PSC
R16_TIM1_ATRLR
R16_TIM1_RPTCR
R16_TIM1_CH1CVR
R16_TIM1_CH2CVR
R16_TIM1_CH3CVR
R16_TIM1_CH4CVR
R16_TIM1_BDTR
R16_TIM1_DMACFGR
R16_TIM1_DMAADR

10.4.1 Control Register 1 (TIM1_CTLR1)

Offset address: 0x00
15 14 13 12
TMR
CAP _CAP
Reserved
LVL _OV_
EN
Bit Name
15 CAPLVL
V1.3
Table 10-2 TIMx internal trigger connections
ITR0(TS=000) ITR1(TS=001)
TIM1
Table 10-3 TIM1-related registers list
Access address
0x40012C00 Control register 1
0x40012C04 Control register 2
0x40012C08 Slave mode control register
0x40012C0C DMA/interrupt enable register
0x40012C10 Interrupt status register
0x40012C14 Event generation register
0x40012C18 Compare/capture control register 1
0x40012C1C Compare/capture control register 2
0x40012C20 Compare/capture enable register
0x40012C24 Counters
0x40012C28 Counting clock prescaler
0x40012C2C Auto-reload value register
0x40012C30 Recurring count value register
0x40012C34 Compare/capture register 1
0x40012C38 Compare/capture register 2
0x40012C3C Compare/capture register 3
0x40012C40 Compare/capture register 4
0x40012C44 Brake and deadband registers
0x40012C48 DMA control register
DMA
0x40012C4C
continuous mode
11 10 9 8
CKD[1:0]
Access
In double-edge capture mode, the capture level
RW
indication is enabled.
ITR2(TS=010)
TIM2
Description
address register
7 6 5
ARP
CMS[1;0] DIR OPM URS UDIS CEN
E
Description
95
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ITR3(TS=011)
Reset value
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
for
0x0000
4 3 2 1
Reset
value
0
0