Adc Module Block Diagram; Adc Configuration; Module Power-Up; Sampling Clock - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual
9.2 Functional description
9.2.1 Module structure
ADC_IN0
ADC_IN1
GPIO
Port
ADC_IN7
Vref
Vcal
TIM1_TRGO
TIM1_CH1
TIM1_CH2
TIM2_TRGO
TIM2_CH1
TIM2_CH2
SWSTART
PD3/PC2
PD1/PA2

9.2.2 ADC configuration

1)

Module power-up

An ADON bit of 1 in the ADC_CTLR2 register indicates that the ADC module is powered up. When the ADC
module enters the power-up state (ADON=1) from the power-down mode (ADON=0), a delay period t
required for the module stabilization time. After that, the ADON bit is written to 1 again and is used as the
start signal for software to start the ADC conversion. By clearing the ADON bit to 0, the current conversion
can be terminated and the ADC module placed in power-down mode, a state in which the ADC consumes
almost no power.
2)

Sampling clock

The register operation of the module is based on the AHBCLK (AHB bus) clock, and the clock reference of
its conversion unit, ADCCLK, is configured by the ADCPRE field of the RCC_CFGR0 register to divide the
frequency, which cannot exceed a maximum of 24MHz.
V1.3
Figure 9-1 ADC module block diagram
Analog Watchdog
High thresh old (10-bit)
Compare
Results
Lo w threshold (10-bit)
AWD=1
EXTSEL[2:0]
EXTTRIG
JEXTSEL[2:0]
TIM1_CH3
TIM1_CH4
TIM2_CH3
TIM2_CH4
JSWSTART
JEXTTRIG
71
Rule channel data
Conversion ends
register (16 bits)
Injection channel data
register (4×16 bits)
-ADC_IOFRx[9:0]
Rule channel
group
Converters
Injection
channel group
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EOC=1
End of Injection convers io n
JEOC=1
ADCCLK
Max=24MHz
Analog to
ADC_SAMPT
Digital
Rx
DMA
Request
STAB
is