Memory And Bus Architecture - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual
Chapter 1 Memory and Bus Architecture
1.1 Bus architecture
The CH32V003 series is designed based on the RISC-V instruction set, and its architecture interacts the core,
arbitration unit, DMA module, SRAM storage and other parts through multiple buses. The design integrates a
general-purpose DMA controller to reduce the CPU load and improve access efficiency, as well as data
protection mechanisms, automatic clock switching protection mechanisms and other measures to increase
system stability. The system block diagram is shown in Figure 1-1.
RISC-V (V2A)
PFIC
1-wire SDI
SWIO
AIN0~AIN7
ETR、ETR2
OPAPx
OPANx
(x=0,1)
OPAO
4 channels, ETR
RX, TX, CTS, RTS, CK
The system is equipped with: Flash access prefetching mechanism to speed up code execution; general-purpose
DMA controller to reduce the CPU burden and improve efficiency; clock tree hierarchy management to reduce
the total power consumption of peripherals, as well as data protection mechanisms, clock security system
protection mechanisms and other measures to increase system stability.
l
The instruction bus (I-Code) connects the core to the FLASH instruction interface and prefetching is done
V1.3
Figure 1-1 CH32V003 system block diagram
I-code Bus
RV32EC
D-code Bus
DMA 7 Channels
SRAM
WWDG
IWDG
EXTI
EXTEN
ADC
Amplify
Compare
TIM2
USART
FLASH
CTRL
Flash
Memory
Reset &
MUX & DIV
*2
AHBCLK
GPIO
IWDG_CLK
PWR_CLK
PWR
I2C
SCL, SDA
AFIO
GPIOA
PA1 ~ PA2
GPIOC
PC0 ~ PC7
GPIOD
PD0 ~ PD7
TIM1
SPI
MOSI,MISO,SCK, NSS
1
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V : 2.7V~5.5V
@VDD
DD
V
SS
SYSCLK
HSI-RC
OSC_IN
HSE
OSC_OUT
LSI-RC
4 channels
3 complementary Channels
ETR, BIKN