Apb1 Peripheral Reset Register; Ahb Peripheral Clock Enable Register - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual
11 TIM1RST
10 Reserved
9 ADC1RST
[8:6] Reserved
5 IOPDRST
4 IOPCRST
3 Reserved
2 IOPARST
1 Reserved
0 AFIORST
3.4.5 APB1 Peripheral reset register (RCC_APB1PRSTR)
Offset address: 0x10
31 30 29 28
PWR
Reserved
RST
15 14 13 12
Reserved
Bit Name
[31:29] Reserved
28 PWRRST
[27:22] Reserved
21 I2C1RST
[20:12] Reserved
11 WWDGRST
[10:1] Reserved
0 TIM2RST
3.4.6 AHB Peripheral clock enable register (RCC_AHBPCENR)
Offset address: 0x14
31 30 29 28
15 14 13 12
V1.3
TIM1 module reset control.
RW
1: Reset module; 0: No effect.
RO Reserved
ADC1 module reset control.
RW
1: Reset module; 0: No effect.
RO Reserved
PD port module reset control for I/O.
RW
1: Reset module; 0: No effect.
PC port module reset control for I/O.
RW
1: Reset module; 0: No effect.
RO Reserved
PA port module reset control for I/O.
RW
1: Reset module; 0: No effect.
RO Reserved
I/O auxiliary function module reset control.
RW
1: Reset module; 0: No effect.
27 26 25 24
Reserved
11 10 9 8
WW
DG
RST
Access
RO Reserved
Power interface module reset control.
RW
1: Reset module; 0: No effect.
RO Reserved
I2C 1 interface reset control.
RW
1: Reset module; 0: No effect.
RO Reserved
Window watchdog reset control.
RW
1: Reset module; 0: No effect.
RO Reserved
Timer 2 module reset control.
RW
1: Reset module; 0: No effect.
27 26 25 24
Reserved
11 10 9 8
Reserved
23 22 21
I2C1
RST
7 6 5
Reserved
Description
23 22 21
7 6 5
21
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20 19 18 17
Reserved
4 3 2 1
Reset
value
20 19 18 17
4 3 2 1
SRA
Reser
M
ved
EN
0
0
0
0
0
0
0
0
0
0
16
0
TIM
2
RST
0
0
0
0
0
0
0
0
16
0
DMA
1
EN