WCH CH32V003 Series Reference Manual page 128

CH32V003 Reference Manual
10 OC2FE
[9:8] CC2S
7 OC1CE
[6:4] OC1M
3 OC1PE
2 OC1FE
[1:0] CC1S
Capture mode (pin direction is input).
Bit Name
[15:12] IC2F
V1.3
written at any time, and the newly written value takes
effect immediately.
Note: Once the LOCK level is set to 3 and CC1S=00,
this bit cannot be modified. PWM mode can be used
only in single pulse mode (OPM=1) without confirming
the pre-load register, otherwise its action is not
determined.
Compare Capture Channel 2 fast enable bit, this bit is
used to speed up the response of the compare capture
channel output to trigger input events.
1: The active edge of the input to the flipflop acts as if
a comparison match has occurred. Therefore, the OC is
set to the comparison level independent of the
comparison result. The delay between the valid edge of
the sample trigger and the output of the compare
RW capture channel 2 is reduced to 3 clock cycles.
0: Based on the value of the counter and compare
capture register 2, compare capture channel 2 operates
normally, even if the flip-flop is open. The minimum
delay to activate the compare capture channel 2 output
is 5 clock cycles when the input of the flipflop has a
valid edge.
OC2FE only works when the channel is configured to
PWM1 or PWM2 mode.
Compare capture channel 2 input selection fields.
00: comparison capture channel 2 is configured as an
output.
01: comparison capture channel 2 is configured as an
input and IC2 is mapped on TI2.
10: comparison capture channel 2 is configured as an
RW input and IC2 is mapped onTI1.
11: Compare Capture Channel 2 is configured as an
input and IC2 is mapped on TRC. This mode works
only when the internal trigger input is selected (by the
TS bit).
Note: Compare Capture Channel 2 is writable only
when the channel is off (when CC2E is zero).
RW Compare capture channel 1 clear enable bit.
RW Compare capture channel 1 mode setting field.
RW Compare capture register 1 preload enable bit.
RW Compare capture channel 1 fast enable bit.
RW Compare capture channel 1 input selection fields.
Access
The input capture filter 2 configuration field, these bits
set the sampling frequency of the TI1 input and the
digital filter length. The digital filter consists of an
event counter, which records N events and then
generates a jump in the output.
0000: no filter, sampled at fDTS.
1000: sampling frequency Fsampling = Fdts/8, N = 6.
RW
0001: sampling frequency Fsampling=Fck_int, N=2.
1001: sampling frequency Fsampling = Fdts/8, N = 8.
0010: sampling frequency Fsampling=Fck_int, N=4.
1010: sampling frequency Fsampling = Fdts/16, N = 5.
0011: sampling frequency Fsampling=f=Fck_int, N=8.
1011: sampling frequency Fsampling = Fdts/16, N = 6.
0100: sampling frequency Fsampling = Fdts/2, N = 6.
128
Description
http://wch.cn
0
0
0
0
0
0
0
Reset
value
0