Compare/Capture Control Register 1 (Tim2_Chctlr1) - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual
11.4.6 Interrupt Status Register (TIM2_INTFR)
Offset address: 0x14
15 14 13 12
Bit Name
[15:7] Reserved
6 TG
5 Reserved
4 CC4G
3 CC3G
2 CC2G
1 CC1G
0 UG

11.4.7 Compare/Capture Control Register 1 (TIM2_CHCTLR1)

Offset address: 0x18
The channel can be used in input (capture mode) or output (compare mode), and the direction of the channel
is defined by the corresponding CCxS bit. The other bits of this register serve different purposes in input and
output modes. OCxx describes the function of the channel in output mode and ICxx describes the function of
V1.3
reinitialized by a trigger event.
11 10 9 8
Reserved
Access
RO Reserved
The trigger event generation bit, which is set by
software and cleared by hardware, is used to generate a
trigger event.
WO 1: Generate a trigger event, TIF is set, and the
corresponding interrupts and DMAs are generated if
enabled.
0: No action.
RO Reserved
Compare capture event generation bit 4. Generate
WO
Compare Capture Event 4.
Compare capture event generation bit 3. Generate
WO
Compare Capture Event 3.
Compare capture event generation bit 2. Generate
WO
Compare Capture Event 2.
Compare capture event generation bit 1. Generate
Compare Capture Event 1. This bit is set by software
and cleared by hardware.
It is used to generate a compare capture event.
1: Generate a compare capture event on compare
capture channel 1.
If compare capture channel 1 is configured as output:
WO set the CC1IF bit. Generate the corresponding
interrupts and DMAs if they are enabled.
If compare capture channel 1 is configured as input: the
current core counter value is captured to compare
capture register 1; set the CC1IF bit and generate the
corresponding interrupts and DMAs if they are enabled.
If CC1IF is already set, set the CC1OF bit.
0: No action.
Update event generation bit to generate an update
event. This bit is set by software and is automatically
cleared by hardware.
1: Initialize the counter and generate an update event.
0: No action.
WO Note: The prescaler counter is also cleared to zero, but
the prescaler factor remains unchanged. The core
counter is cleared if in centrosymmetric mode or
incremental counting mode; if in decremental counting
mode, the core counter takes the value of the reload
value register.
7 6 5
TG Reserved CC4G CC3G CC2G CC1G UG
Description
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4 3 2 1
Reset
value
0
0
0
0
0
0
0
0
0