Exception Entry Base Address Register (Mtvec); Stk Register Description; System Count Control Register (Stk_Ctlr) - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual
Bit Name
[31:2] Reserved
1 INESTEN
0 HWSTKEN

6.5.3.2 Exception entry base address register (MTVEC)

CSR address: 0x305
31 30 29 28
15 14 13 12
Bit Name
[31:2] BASEADDR[31:2]
1 MODE1
0 MODE0

6.5.4 STK register description

Name
R32_STK_CTLR
R32_STK_SR
R32_STK_CNTL
R32_STK_CMPLR

6.5.4.1 System count control register (STK_CTLR)

Offset address: 0x00
31 30 29 28
SWIE
15 14 13 12
V1.3
Access
MRO Reserved
Interrupt nesting enable.
MRW 0: interrupt nesting function off.
1: Interrupt nesting function is enabled.
Hardware stack enable.
MRW 0: hardware stacking function off.
1: Hardware stacking function is enabled.
27 26 25 24
BASEADDR[31:16]
11 10 9 8
BASEADDR[15:2]
Access
MRW Interrupt vector table base address.
Interrupt vector table identifies patterns.
0: identification by jump instruction,
limited range, support for non-jump
MRW
instructions.
1: Identify by absolute address, support
full range, but must jump.
Interrupt or exception entry address mode
selection.
MRW 0: use of a unified entry address.
1: Address offset based on interrupt number
*4.
Table 6-5 STK-related registers list
Access address
0xE000F000 System count control register
0xE000F004 System count status register
0xE000F008 System counter low register
0xE000F010 Counting comparison low register
27 26 25 24
11 10 9 8
Reserved
Description
23 22 21
7 6 5
Description
Description
23 22 21
Reserved
7 6 5
47
http://wch.cn
T
EN
Reset value
0
0
0
20 19 18 17
4 3 2 1
MODE
1
Reset value
0
0
0
Reset value
0x00000000
0x00000000
0x00000000
0x00000000
20 19 18 17
4 3 2 1
STCL
STRE STIE STE
K
TKE
N
16
0
MOD
E0
16
0