WCH CH32V003 Series Reference Manual page 115

CH32V003 Reference Manual
Figure 11-3 Block diagram of the structure of the comparison capture channel
TI1
Filter
f
downcounter
DTS
ICF[3:0]
TIMx_CHCTLR1
Read CCR1H
S
read_in_progress
Read CCR1L
R
CC1S[1]
mode
CC1S[0]
IC1PS
CC1E
CC1G
TIM1_SWEVGR
ETRF
>
CNT CCR1
CNT = CCR1
TIMx_CHCTLR1
The signal is input from the channel x pin and optionally made as TIx (the source of TI1 can be more than
CH1, see block diagram 10-1 of the timer), TI1 is passed through the filter (ICF[3:0]) to generate TI1F, and
then divided into TI1F_Rising and TI1F_Falling through the edge detector, these two signals are selected
(CC1P) to generate TI1FP1, TI1FP1 and TI2FP1 from channel 2 are sent together to CC1S to select to become
IC1, which is sent to the comparison capture register after ICPS dividing.
The compare capture register consists of a preload register and a shadow register, and the read/write process
operates only on the preload register. In capture mode, the capture occurs on the shadow register and is then
copied to the preload register; in compare mode, the contents of the preload register are copied to the shadow
register, and then the contents of the shadow register are compared to the core counter (CNT).
11.3 Functionality and implementation
The complex functions of a general-purpose timer are implemented by manipulating the timer's compare
capture channel, clock input circuitry, and counter and peripheral components. The clock input to the timer
can be derived from multiple clock sources including the input to the compare capture channel. The operation
V1.3
TI1F_Rising
TI1F
Edge
TI1F_Falling
detector
CC1P/CC1NP
TIMx_CCER
TI2F_Rising
(from channel 2)
TI2F_Falling
(from channel 2)
MCU-peripheral interface
Capture/compare preload register
capture_transfer
Input
Capture/compare shadow register
Capture
To the master mode
controller
Output
OC1REF
mode
controller
OC1M[2:0]
TI1F_ED
To the slave mode controller
0
TI1FP1
01
1
TI2FP1
10
TRC
11
(from slave mode
controller)
0
CC1S[1:0] ICPS[1:0]
1
TIMx_CHCTLR1
APB Bus
write_in_progress
compare_transfer
Comparator
Counter
0
1
CC1P
TIM1_CCER
115
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IC1 Divider
/1,/2,/4,/8
CC1E
TIMx_CCER
Write CCR1H
S
Write CCR1L
R
Output
CC1S[1]
mode
CC1S[0]
OC1PE
OC1PE
UEV
TIMx_CHCTLR1
(from time
base unit)
Output
OC1
enable
circuit
CC1E
TIM1_CCER