Interrupt Status Register (Tim2_Intfr) - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual

11.4.5 Interrupt Status Register (TIM2_INTFR)

Offset address: 0x10
15 14 13 12
Reserved CC4OF CC3OF CC2OF CC1OF Reserved TIF Reserved CC4IF CC3IF CC2IF CC1IF UIF
Bit Name
[15:13] Reserved
12 CC4OF
11 CC3OF
10 CC2OF
9 CC1OF
[8:7] Reserved
6 TIF
5 Reserved
4 CC4IF
3 CC3IF
2 CC2IF
1 CC1IF
0 UIF
V1.3
11 10 9
Access
RO Reserved
WO Compare capture channel 4 to repeat capture flag bits.
WO Compare capture channel 3 to repeat capture flag bits.
WO Compare capture channel 2 to repeat capture flag bits.
The compare capture channel 1 repeat capture flag bit
is used only when the compare capture channel is
configured for input capture mode. This flag is set by
hardware and a software write of 0 clears this bit.
WO
1: the value of the counter is captured into the capture
comparison register when the status of CC1IF has been
set.
0: No duplicate captures are generated.
RO Reserved
Trigger interrupt flag bit, when a trigger event occurs
by hardware to this location bit, by software to clear.
Trigger events include the detection of a valid edge at
WO the TRGI input from a mode other than gated, or any
edge in gated mode.
1: Trigger event generation.
0: No trigger event is generated.
RO Reserved
WO Compare capture channel 4 interrupt flag bits.
WO Compare capture channel 3 interrupt flag bits.
WO Compare capture channel 2 interrupt flag bits.
Compare capture channel 1 interrupt flag bits.
If the compare capture channel is configured in output
mode, this bit is set by hardware when the counter value
matches the compare value, except in centrosymmetric
mode. This bit is cleared by software.
1: The value of the core counter matches the value of
compare capture register 1;
WO 0: No match occurs.
If compare capture channel 1 is configured in input
mode, this bit is set by hardware when a capture event
occurs and it is cleared by software or by reading the
compare capture register.
1: the counter value has been captured compare capture
register 1.
0: No input capture is generated.
Update interrupt flag bit, this bit is set by hardware
when an update event is generated and cleared by
software.
1: Update interrupt generation.
0: No update event is generated.
WO The following scenarios generate update events.
If UDIS = 0, when the repeat counter value overflows
or underflows.
If URS = 0, UDIS = 0, when the UG bit is set, or when
the counter core counter is reinitialized by software.
If URS = 0, UDIS = 0, when the counter CNT is
8 7 6 5
Description
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4 3 2 1
Reset
value
0
0
0
0
0
0
0
0
0
0
0
0
0
0