Slave Mode Control Register (Tim1_Smcfgr) - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual
3 CCDS
2 CCUS
1 Reserved
0 CCPC

10.4.3 Slave Mode Control Register (TIM1_SMCFGR)

Offset address: 0x08
15 14 13 12
ETP ECE ETPS[1:0]
V1.3
the synchronization information (TRGO) sent to the
slave timer in master mode. The possible combinations
are as follows.
000: The UG bit of the Reset-TIMx_EGR register is
used as the trigger output (TRGO). In the case of a reset
generated by a trigger input (from a mode controller in
reset mode), there is a delay in the signal on TRGO
relative to the actual reset.
001: Enable - The counter enable signal CNT_EN is
used as a trigger output (TRGO). Sometimes it is
necessary to start multiple timers at the same time or to
control the enable from timers over a period of time.
The counter enable signal is generated by the logical or
of the trigger input signal in CEN control bit and gated
mode. When the counter enable signal is controlled by
a trigger input, there is a delay on TRGO unless
master/slave mode is selected (see the description of the
MSM bit in the TIMx_SMCR register).
010: Update - The update event is selected as a trigger
input (TRGO). For example, the clock of a master timer
may be used as a prescaler for a slave timer.
011: comparison pulse - on the occurrence of a capture
or a successful comparison, when the CC1IF flag is to
be set (even if it is already high), the trigger output
sends a positive pulse (TRGO).
100: The comparison-OC1REF signal is used as a
trigger output (TRGO).
101: The comparison-OC2REF signal is used as a
trigger output (TRGO).
110: The comparison-OC3REF signal is used as a
trigger output (TRGO).
111: The compare-OC4REF signal is used as the trigger
output (TRGO).
Capture the DMA selection for comparison.
1: Sending a DMA request for CHxCVR when an
RW update event occurs.
0: Generate a DMA request for CHxCVR when
CHxCVR occurs.
Compare capture control update selection bits.
1: if CCPC is set, they can be updated by setting the
COM bit or a rising edge on TRGI.
RW 0: If the CCPC is set, they can only be updated by
setting the COM bit.
Note: This bit only works for channels with
complementary outputs.
RO Reserved
Compare capture preload control bits.
1: the CCxE, CCxNE and OCxM bits are preloaded and
when this bit is set they are only updated when the
RW COM bit is set.
0: CCxE, CCxNE and OCxM bits are not preloaded.
Note: This bit only works for channels with
complementary outputs.
11 10 9 8
ETF[3:0]
7 6 5 4
MSM TS[2:0]
98
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0
0
0
0
3 2 1
Reserved SMS[2:0]
0