Usart Control Register 2 (Usart_Ctlr2) - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual

12.10.5 USART Control register 2 (USART_CTLR2)

Offset address: 0x10
31 30 29 28
15 14 13 12
Reser LINE
STOP
ved N
Bit Name
[31:15] Reserved
14 LINEN
[13:12] STOP
11 CLKEN
10 CPOL
9 CPHA
8 LBCL
V1.3
1: Send; 0: Do not send.
27 26 25 24
Reserved
11 10 9 8
CLK CPO CPH LBC
EN L A L
Access
RO Reserved
LIN mode enable, set to enable LIN mode. The
LIN mode enables the capability to send LIN
RW Synch Breaks using the SBK bit in the
USART_CR1 register, and to detect LIN Sync
breaks.
STOP bits.
These bits are used for programming the stop bits.
00: 1 Stop bit
RW
01: 0.5 Stop bit
10: 2 Stop bits
11: 1.5 Stop bit
Clock enable.
This bit allows the user to enable the CK pin.
RW
0: CK pin disabled
1: CK pin enabled
Clock polarity
This bit allows the user to select the polarity of the
clock output on the CK pin in synchronous mode.
It works in conjunction with the CPHA bit to
produce the desired clock/data relationship
RW 0: Steady low value on CK pin outside
transmission window.
1: Steady high value on CK pin outside
transmission window.
Note: This bit cannot be modified after enabling
transmit.
Clock phase
This bit allows the user to select the phase of the
clock output on the CK pin in synchronous mode.
It works in conjunction with the CPOL bit to
produce the desired clock/data relationship
RW 0: The first clock transition is the first data capture
edge.
1: The second clock transition is the first data
capture edge.
Note: This bit cannot be modified after enabling
transmit.
Last bit clock pulse
This bit allows the user to select whether the clock
pulse associated with the last data bit transmitted
RW (MSB) has to be output on the CK pin in
synchronous mode.
0: The clock pulse of the last data bit is not output
to the CK pin
23 22 21
7 6 5
Reser LBDI LBD Reser
ved E L
Description
141
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20 19 18 17
4 3 2 1
ADD[3:0]
ved
Reset value
0
0
0
0
0
0
0
16
0