Clock Security System; Clock Control Register (Rcc_Ctlr); Microcontroller Clock Output (Mco); Rcc-Related Registers List - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual

3.3.5.4 Microcontroller clock output (MCO)

The microcontroller allows outputting clock signals to the MCO pins. The following 4 clock signals can be
selected as MCO clock outputs by configuring the multiplexed push-pull output mode in the corresponding
GPIO port registers by configuring the MCO[2:0] bits of the RCC_CFGR0 register.
l System clock (SYSCLK) output
l HSI clock output
l
HSE clock output
l PLL clock output after 2X frequency

3.3.6 Clock security system

The clock safety system is an operational protection mechanism for the controller that switches to the HSI
clock in the event of an HSE clock transmit failure and generates an interrupt notification to allow the
application software to complete a rescue operation.
The clock security system is activated by setting CSSON position 1 of the RCC_CTLR register. At this point,
the clock monitor will be enabled after the HSE oscillator start (HSERDY=1) delay and will be turned off after
the HSE clock is turned off. Once the HSE clock fails during system operation, the HSE oscillator will be
turned off, the clock failure event will be sent to the brake input of the advanced-control timer (TIM1) and a
clock safety interrupt will be generated with CSSF position 1 and the application enters the NMI non-maskable
interrupt. By setting the CSSC bit, the CSSF bit flag can be cleared and the NMI interrupt pending bit can be
undone.
If the current HSE is used as the system clock, or if the current HSE is used as the PLL input clock and the
PLL is used as the system clock, the clock safety system will automatically switch the system clock to the HSI
oscillator and turn off the HSE oscillator and PLL in case of HSE failure.
3.4 Register description
Name
R32_RCC_CTLR
R32_RCC_CFGR0
R32_RCC_INTR
R32_RCC_APB2PRSTR
R32_RCC_APB1PRSTR
R32_RCC_AHBPCENR
R32_RCC_APB2PCENR
R32_RCC_APB1PCENR
R32_RCC_RSTSCKR

3.4.1 Clock control register (RCC_CTLR)

Offset address: 0x00
31 30 29 28
Reserved
15 14 13 12
HSICAL[7:0]
Bit Name
[31:26] Reserved
V1.3
Table 3-1 RCC-related registers list
Access address
0x40021000 Clock control register
0x40021004 Clock configuration register 0
0x40021008 Clock interrupt register
0x4002100C APB2 peripheral reset register
0x40021010 APB1 peripheral reset register
0x40021014 AHB peripheral clock enable register
0x40021018 APB2 peripheral clock enable register
0x4002101C APB1 peripheral clock enable register
0x40021024 Control/status register
27 26 25 24
PLL PLL
RDY ON
11 10 9 8
Access
RO Reserved
Description
23 22 21
Reserved
7 6 5
HSITRIM[4:0]
Description
16
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Reset value
0x0000xx83
0x00000000
0x00000000
0x00000000
0x00000000
0x00000014
0x00000000
0x00000000
0x0C000000
20 19 18 17
CSSO HSE HSE
N BYP RDY
4 3 2 1
Reser HSI
ved RDY
Reset
value
16
HSE
ON
0
HSIO
N
0