Usart Data Register (Usart_Datar) - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual
1 FE
0 PE

12.10.2 USART Data register (USART_DATAR)

Offset address: 0x04
31 30 29 28
15 14 13 12
Reserved
Bit Name
[31:9] Reserved
[8:0] DR
12.10.3 USART Status register (USART_STATR)
Offset address: 0x08
31 30 29 28
15 14 13 12
Bit Name
[31:16] Reserved
[15:4] DIV_ Mantissa
[3:0] DIV_ Fraction
V1.3
interrupt. If the EIE bit is set, the FE flag position
bit generates an interrupt in multi-buffer
communication mode.
Frame error flag. This bit will be set by hardware
when a synchronization error, excessive noise or
disconnect character is detected. Reading this bit
and then reading the data register operation will
reset this bit.
RO
1: Frame error detected.
0: No frame error detected.
Note: This bit will not generate an interrupt. If the
EIE bit is set, the FE flag position bit will generate
an interrupt in multi-buffer communication mode.
Checksum error flag. In receive mode, hardware
sets this bit if a parity check error is generated. A
read of this bit and then a read of the data register
operation resets this bit. Before clearing this bit,
RO software must wait for the RXNE flag bit to be set.
If the PEIE has been set previously, then this bit
being set generates a corresponding interrupt.
1: A parity error.
0: No inspection error.
27 26 25 24
Reserved
11 10 9 8
Access
RO Reserved
Data register. This register is actually the receive
data register (RDR) and send register (TDR) two
RW registers composed of DR read and write operation
start is read receive register (RDR) and write send
register (TDR) respectively.
27 26 25 24
Reserved
11 10 9 8
DIV_Mantissa[11:0]
Access
RO Reserved
These 12 bits define the integer part of the dividing
RW
factor of the frequency divider.
These 4 bits define the fractional part of the
RW
dividing factor of the frequency divider.
23 22 21
7 6 5
DR[8:0]
Description
23 22 21
7 6 5
Description
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0
0
20 19 18 17
4 3 2 1
Reset value
0
X
20 19 18 17
4 3 2 1
DIV_Fraction[3:0]
Reset value
0
0
0
16
0
16
0