Dedicated Csr Registers; Interrupt System Control Register (Intsyscr) - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual
SYS
RESE
T
15 14 13 12
Bit Name
31 SYSRESET
[30:6] Reserved
5 SETEVENT
4 SEVONPEND
3 WFITOWFE
2 SLEEPDEEP
1 SLEEPONEXIT
0 Reserved

6.5.3 Dedicated CSR registers

A number of Control and Status Registers (CSRs) are defined in the RISC-V architecture to configure or
identify or record the operational status. The CSR registers are internal to the core and use a dedicated 12-bit
address space; the CH32V003 chip adds a number of vendor-defined registers in addition to the standard
registers defined in the RISC-V privileged architecture document, which need to be accessed using the csr
instruction.
Note: These registers are labeled "MRW,MRO,MRW1" and require the system to be in machine mode to access
them.

6.5.3.1 Interrupt system control register (INTSYSCR)

CSR address: 0x804
31 30 29 28
15 14 13 12
V1.3
11 10 9 8
Reserved
Access
System reset, clear 0 automatically. write 1
WO valid, write 0 invalid, same effect as
PFIC_CFGR register.
RO Reserved
WO Set the event to wake up the WFE case.
When an event occurs or interrupts a
pending state, the system can be woken up
from after the WFE instruction, or if the
WFE instruction is not executed, the
system will be woken up immediately after
RW the next execution of the instruction.
1: enabled events and all interrupts
(including unenabled interrupts) can wake
up the system.
0: Only enabled events and enabled
interrupts can wake up the system.
Execute the WFI command as if it were a
WFE.
RW 1: treat the subsequent WFI instruction as a
WFE instruction.
0: No effect.
Low-power mode of the control system.
RW
1：deep sleep
System status after control leaves the
interrupt service program.
RW
1: The system enters low-power mode.
0: The system enters the main program.
RO Reserved
27 26 25 24
Reserved
11 10 9 8
Reserved
Reserved
7 6 5
SET SEV
EVE ONPE
NT
Description
0：sleep
23 22 21
7 6 5
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4 3 2 1
WFIT SLEE SLEEP
O P ONEX
ND WFE DEEP IT
Reset value
0
0
0
0
0
0
0
0
20 19 18 17
4 3 2 1
INES HWS
0
Reser
ved
16
0