Pfic Registers; Software Interrupt Event Register (Exti_Swievr); Interrupt Flag Register (Exti_Intfr) - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual
Reserved
Bit Name
[31:10] Reserved
[9:0] TRx

6.5.1.5 Software interrupt event register (EXTI_SWIEVR)

Offset address: 0x10
31 30 29 28
15 14 13 12
Reserved
Bit Name
[31:10] Reserved
[9:0] SWIERx

6.5.1.6 Interrupt flag register (EXTI_INTFR)

Offset address: 0x14
31 30 29 28
15 14 13 12
Reserved
Bit Name
[31:10] Reserved
[9:0] IFx

6.5.2 PFIC registers

Name
R32_PFIC_ISR1
R32_PFIC_ISR2
R32_PFIC_IPR1
R32_PFIC_IPR2
R32_PFIC_ITHRESDR
R32_PFIC_CFGR
V1.3
TR9 TR8 TR7 TR6 TR5 TR4 TR3 TR2 TR1 TR0
Access
RO Reserved
Enable falling edge triggering of external interrupt
channel x.
RW
0: Disable falling edge triggering for this channel.
1: Enable falling edge triggering for this channel.
27 26 25 24
Reserved
11 10 9 8
SWIE SWIE
R 9 R 8
Access
RO Reserved
A software interrupt is set on the corresponding
externally triggered interrupt channel. Setting it
here causes the interrupt flag bit (EXTI_INTFR)
RW to correspond to the position bit, and if interrupt
enable
(EXTI_EVENR) is on, then an interrupt or event
will be generated.
27 26 25 24
Reserved
11 10 9 8
IF9 IF8
Access
RO Reserved
The interrupt flag bit, this location bit flag
W1 indicates that the corresponding external interrupt
has occurred. A write of 1 clears this bit.
Table 6-4 List of PFIC-related registers
Access address
0xE000E000 PFIC interrupt enable status register 1
0xE000E004 PFIC interrupt enable status register 2
0xE000E020 PFIC interrupt pending status register 1
0xE000E024 PFIC interrupt pending status register 2
PFIC
0xE000E040
configuration register
0xE000E048 PFIC interrupt configuration register
Description
23 22 21
7 6 5
SWIE SWIE SWIE SWIE
R 7 R 6 R 5 R 4
Description
(EXTI_INTENR) or
23 22 21
7 6 5
IF7 IF6 IF5 IF4
Description
Description
interrupt priority
36
http://wch.cn
Reset value
0
0
20 19 18 17
4 3 2 1
SWIE SWIE SWIE
R 3 R 2 R 1
Reset value
0
0
event enable
20 19 18 17
4 3 2 1
IF3 IF2 IF1
Reset value
0
X
Reset value
0x0000000C
0x00000000
0x00000000
0x00000000
threshold
0x00000000
0x00000000
16
0
SWIE
R 0
16
0
IF0