Dma Channel X Number Of Data Register (Dma_Cntrx) - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual
7 MINC
6 PINC
5 CIRC
4 DIR
3 TEIE
2 HTIE
1 TCIE
0 EN
8.3.4 DMA Channel x number of data register (DMA_CNTRx)(x=1/2/3/4/5/6/7 )
Offset address: 0x0C + (x-1)*20 + (y-1)*0x400
31 30 29 28
15 14 13 12
Bit Name
[31:16] Reserved
[15:0] NDT
Note: This register can only be changed when EN=0; when EN=1, it is a read-only register, indicating the
current number of pending transfers. When the register content is 0, no data transmission will occur regardless
of whether the channel is on or off.
V1.3
Memory address incremental incremental mode enable.
1: Enable incremental memory address increment
RW
operation.
0: Memory address remains unchanged operation.
Peripheral address incremental incremental mode enable.
1: Enable incremental incremental operation of the
RW
peripheral address.
0: Peripheral address remains unchanged operation.
DMA channel cyclic mode enable.
RW 1: Enables cyclic operation.
0: Perform a single operation.
Data transfer direction.
RW 1: Read from memory.
0: Read from peripheral.
Transmission error interrupt enable control.
RW 1: Enable transmission error interrupts.
0: Disable transmission error interrupt.
Transmission over half interrupt enable control.
RW 1: Enable the transmission over half interrupt.
0: Disable the transmission over half interrupt.
Transmission completion interrupt enable control.
RW 1: Enable the transmission completion interrupt.
0: Disable the transmission completion interrupt.
Channel enable control.
1: Channel on; 0: Channel off.
RW When a DMA transfer error occurs, the hardware
automatically clears this bit to 0 and shuts down the
channel.
27 26 25 24
Reserved
11 10 9 8
NDT[15:0]
Access
RO Reserved
Number of data transfers, range 0-65535.
This register can only be written when the channel is not
operating (EN=0 for DMA_CFGRx). After the channel is
turned on this register becomes read-only and indicates the
RW number of remaining pending transfers (the register
content is decremented after each DMA transfer).
When the channel is in cyclic mode, the contents of the
register will be automatically reloaded to the previously
configured value.
23 22 21
7 6 5
Description
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20 19 18 17
4 3 2 1
Reset
value
0
0
0
0
0
0
0
0
16
0
0
0