WCH CH32V003 Series Reference Manual page 155

CH32V003 Reference Manual
0 SB
13.11.7 I2C Status register 2(I2C_STAR2)
Offset address: 0x18
15 14 13 12
PEC[7:0]
Bit Name
[15:8] PEC
7 DUALF
[6:5] Reserved
4 GENCALL
3 Reserved
2 TRA
1 BUSY
0 MSL
V1.3
byte. For 7-bit addressing, the bit is set after the
ACK of the byte.
0：No end of address transmission.
In Slave mode:
1：Received address matched.
0：Address mismatched or not received.
Start bit. Cleared by software by reading the SR1
register followed by writing the DR register, or by
hardware when PE=0
RO
1：Start condition generated.
0：No Start condition.
11 10 9 8
Access
Packet error checking bit. When PEC is enabled
RO
(ENPEC is set), this field holds the value of PEC.
Dual flag. Cleared by hardware after a Stop
condition or repeated Start condition, or when
PE=0.
RO
1：Received address matched with OAR2.
0：Received address matched with OAR1.
RO Reserved
General call address bit. Cleared by hardware
after a Stop condition or repeated Start condition,
or when PE=0.
RO
1：General
ENGC=1.
0：No General Call.
RO Reserved
Transmitter/receiver bit. It is cleared by hardware
after detection of Stop condition (STOPF=1),
repeated Start condition, loss of bus arbitration
(ARLO=1), or when PE=0.
RO
1：Data bytes transmitted.
0：Data bytes received.
This bit is set depending on the R/W bit of the
address byte.
Bus busy bit. Cleared by hardware on detection of
a Stop condition. This information is still updated
when the interface is disabled (PE=0).
RO
1：Communication ongoing on the bus: low level
present in SDA or SCL.
0：No communication on the bus.
Master/slave bit. Set by hardware as soon as the
interface is in Master mode (SB=1). Cleared by
RO hardware after detecting a Stop condition on the
bus or a loss of arbitration (ARLO=1), or by
hardware when PE=0.
7 6 5
GEN
DUA
Reserved CAL
LF
Description
Call Address
155
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0
4 3 2 1
Reser BUS
TRA
ved Y
L
Reset value
0
0
0
0
received when
0
0
0
0
0
MSL