WCH CH32V003 Series Manuals

Manuals and User Guides for WCH CH32V003 Series. We have 1 WCH CH32V003 Series manual available for free PDF download: Reference Manual

WCH CH32V003 Series Reference Manual (182 pages)

Brand: WCH | Category: Microcontrollers | Size: 2.12 MB

Overview
1
Memory and Bus Architecture
2
Memory Image
4
Memory Allocation
5
Power Control (PWR)
6
Power Management
6
Power-On Reset and Power-Down Reset
6
Programmable Voltage Detector
6
Low-Power Modes
7
Low-Power Configuration Options
8
Sleep Mode
8
Standby Mode
8
Auto-Wakeup (AWU)
8
Register Description
9
Power Control Register (PWR_CTLR)
9
Power Control/Status Register (PWR_CSR)
9
Auto-Wakeup Control/Status Register (PWR_AWUCSR)
10
Auto-Wakeup Window Comparison Value Register (PWR_ AWUWR)
10
Reset and Clock Control (RCC)
12
Power Reset
12
System Reset
12
System Clock Structure
14
High-Speed Clock (HSI/HSE)
15
Low-Speed Clock (LSI)
16
PLL Clock
16
Bus/Peripheral Clock
16
Independent Watchdog Clock
16
Clock Security System
17
Clock Control Register (RCC_CTLR)
17
Microcontroller Clock Output (MCO)
17
RCC-Related Registers List
17
Clock Configuration Register0 (RCC_CFGR0)
19
Clock Interrupt Register (RCC_INTR)
20
APB2 Peripheral Reset Register (RCC_APB2PRSTR)
21
APB1 Peripheral Reset Register
22
AHB Peripheral Clock Enable Register
22
APB2 Peripheral Clock Enable Register
23
APB1 Peripheral Clock Enable Register
24
Control/Status Register
24
Independent Watchdog (IWDG)
26
Enable Independent Watchdog
26
Watchdog Configuration
26
Control Register (IWDG_CTLR)
27
Debug Mode
27
Prescaler Register
27
Reload Register
28
Status Register
28
Window Watchdog (WWDG)
29
Enable Window Watchdog
29
Watchdog Reset
30
Wake up in Advance
30
WWDG-Related Registers List
31
Control Register (WWDG_CTLR)
31
Configuration Register (WWDG_CFGR)
31
Status Register (WWDG_STATR)
32
Interrupt and Events (PFIC)
33
PFIC Controller
33
System Timer
33
Vector Table of Interrupts and Exceptions
33
External Interrupt and Event Controller (EXTI)
34
Wake-Up Event
34
External Interrupt (EXTI) Interface Block Diagram
34
External Event Mapping
35
EXTI Registers
35
EXTI Interrupt Mapping
35
Interrupt Enable Register (EXTI_INTENR)
36
Event Enable Register (EXTI_EVENR)
36
Rising Edge Trigger Enable Register (EXTI_RTENR)
36
Falling Edge Trigger Enable Register (EXTI_FTENR)
36
PFIC Registers
37
Software Interrupt Event Register (EXTI_SWIEVR)
37
Interrupt Flag Register (EXTI_INTFR)
37
PFIC Interrupt Enable Status Register 1
38
PFIC Interrupt Enable Status Register 2
39
PFIC Interrupt Pending Status Register 1
39
PFIC Interrupt Pending Status Register 2
40
PFIC Interrupt Priority Threshold Configuration Register
40
PFIC Interrupt Configuration Register (PFIC_CFGR)
40
PFIC Interrupt Global Status Register (PFIC_GISR)
41
PFIC VTF Interrupt ID Configuration Register (PFIC_VTFIDR)
41
PFIC VTF Interrupt 0 Address Register (PFIC_VTFADDRR0)
41
PFIC VTF Interrupt 1 Address Register (PFIC_VTFADDRR1)
42
PFIC Interrupt Enable Setting Register 1 (PFIC_IENR1)
42
PFIC Interrupt Enable Setting Register 2 (PFIC_IENR2)
42
PFIC Interrupt Enable Clear Register 1 (PFIC_IRER1)
43
PFIC Interrupt Enable Clear Register 2 (PFIC_IRER2)
43
PFIC Interrupt Pending Setup Register 1 (PFIC_IPSR1)
43
PFIC Interrupt Pending Setup Register 2 (PFIC_IPSR2)
44
PFIC Interrupt Pending Clear Register 1 (PFIC_IPSR1)
44
PFIC Interrupt Pending Clear Register 2 (PFIC_IPSR2)
45
PFIC Interrupt Activation Status Register 1 (PFIC_IACTR1)
45
PFIC Interrupt Activation Status Register 2 (PFIC_IACTR2)
46
PFIC Interrupt Priority Configuration Register (Pfic_Ipriorx)
46
PFIC System Control Register (PFIC_SCTLR)
46
Dedicated CSR Registers
47
Interrupt System Control Register (INTSYSCR)
47
Exception Entry Base Address Register (MTVEC)
48
STK Register Description
48
System Count Control Register (STK_CTLR)
48
System Count Status Register (STK_SR)
49
System Counter Register (STK_CNTL)
49
Counting Comparison Register (STK_CMPLR)
50
GPIO and Alternate Function (GPIO/AFIO)
51
GPIO Module Basic Structure Block Diagram
51
GPIO Initialization Function
52
External Interrupts
52
Multiplexing Functions
52
GPIO Module Input Configuration Structure Block Diagram
52
GPIO Module Output Configuration Structure Block Diagram
53
Multiplexing Function Configuration
53
Analog Input Configuration
54
GPIO Settings for Peripherals
54
GPIO Register Description
55
Port Configuration Register Low (Gpiox_Cfglr)
56
Port Input Register (Gpiox_Indr)
56
Port Output Register (Gpiox_Outdr) (X=A/C/D)
57
Port Reset/Set Register (Gpiox_Bshr) (X=A/C/D)
57
Port Reset Register (Gpiox_Bcr) (X=A/C/D)
57
AFIO Register Description
58
Port Configuration Lock Register (Gpiox_Lckr) (X=A/C/D)
58
Remap Register 1 (AFIO_PCFR1)
58
External Interrupt Configuration Register 1 (AFIO_EXTICR)
60
Direct Memory Access Control (DMA)
62
DMA Channel Processing
62
Arbitration Priority
62
DMA Configuration
62
Programmable Total Data Transfer Size/Data Bit Width/Alignment
63
Circular Mode
63
DMA Processing Status
63
DMA Request Mapping
64
DMA-Related Registers List
65
DMA1 Request Image
65
DMA1 Peripheral Mapping Table for each Channel
65
DMA Interrupt Status Register (DMA_INTFR)
66
DMA Interrupt Flag Clear Register (DMA_INTFCR)
66
DMA Channel X Configuration Register (Dma_Cfgrx)
67
DMA Channel X Number of Data Register (Dma_Cntrx)
68
DMA Channel X Peripheral Address Register (Dma_Paddrx)
69
DMA Channel X Memory Address Register (Dma_Maddrx)
69
Analog-To-Digital Converter (ADC)
70
ADC Module Block Diagram
71
ADC Configuration
71
Module Power-Up
71
Sampling Clock
71
Channel Configuration
72
Calibration
72
Programmable Sampling Time
72
Data Alignment
72
External Trigger Source
73
Conversion Mode
73
Single Single-Channel Conversion Mode
74
Single Scan Mode Conversion
74
Single Intermittent Mode Conversion
75
Trigger Injection
75
Auto-Injection
75
Simulating a Watchdog
76
Continuous Conversion
76
Analog Watchdog Threshold Area
76
Analog Watchdog Channel Selection
76
ADC-Related Registers List
77
ADC Status Register (ADC_STATR)
77
ADC Control Register 1 (ADC_CTLR1)
78
ADC Control Register 2 (ADC_CTLR2)
79
ADC Sample Time Configuration Register 1 (ADC_SAMPTR1)
81
ADC Sample Time Configuration Register 2 (ADC_SAMPTR2)
81
ADC Injected Channel Data Offset Register X (Adc_Iofrx)
81
ADC Watchdog High Threshold Register (ADC_WDHTR)
82
ADC Watchdog Low Threshold Register (ADC_WDHTR)
82
ADC Regular Sequence Register 1(ADC_RSQR1)
82
ADC Regular Sequence Register 2(ADC_RSQR2)
83
ADC Regular Sequence Register 3(ADC_RSQR3)
83
ADC Injected Sequence Register (ADC_ISQR)
84
ADC Injected Data Register (Adc_Idatarx)
84
ADC Regular Data Register (ADC_RDATAR)
84
ADC Delayed Data Register (ADC_DLYR)
85
Advanced-Control Timer (ADTM)
86
Block Diagram of Advanced-Control Timer Structure
87
Clock Input
88
Internal Clock Source (CK_INT)
88
External Clock Source Mode1/2
88
Block Diagram of CK_PSC Source for Advanced-Control Timer
88
Counters and Peripherals
89
Comparing Capture Channels and Perimeters
89
Encoder Mode
89
Block Diagram of the Structure of the Comparison Capture Channel
90
Functionality and Implementation
91
Input Capture Mode
91
Compare Output Modes
91
Forced Output Mode
92
PWM Input Mode
92
PWM Output Mode
92
Complementary Outputs and Dead Zones
92
Brake Signal
93
Single Pulse Mode
93
Complementary Outputs and Deadband
93
Generation of Single Pulse
94
TIM1-Related Registers List
95
Timer Synchronization Mode
95
Control Register 1 (TIM1_CTLR1)
95
Control Register 2 (TIM1_CTLR2)
97
Slave Mode Control Register (TIM1_SMCFGR)
98
Dma/Interrupt Enable Register (TIM1_DMAINTENR)
100
Interrupt Status Register (TIM1_INTFR)
101
Event Generation Register (TIM1_SWEVGR)
102
Compare/Capture Control Register 1 (TIM1_CHCTLR1)
104
Compare/Capture Control Register 2 (TIM1_CHCTLR2)
106
Compare/Capture Enable Register 2 (TIM1_CCER)
107
Counter for Advanced-Control Timer (TIM1_CNT)
108
Counting Clock Prescaler (TIM1_PSC)
108
Auto-Reload Value Register (TIM1_ATRLR)
108
Repeat Count Value Register (TIM1_RPTCR)
108
Compare/Capture Register
109
Brake and Deadband Register
109
DMA Control Register (TIM1_DMACFGR)
110
General-Purpose Timer (GPTM)
112
Difference between General-Purpose Timer and Advanced-Control Timer
113
General Timer CK_PSC Source Block Diagram
113
Comparing Capture Channels
114
Compare Output Mode
116
TIM2-Related Registers List
119
Control Register 1 (TIM2_CTLR1)
119
Control Register 2 (TIM2_CTLR2)
121
Slave Mode Control Register (TIM2_SMCFGR)
122
Interrupt Status Register (TIM2_INTFR)
125
Compare/Capture Control Register 1 (TIM2_CHCTLR1)
126
Compare/Capture Control Register 2 (TIM2_CHCTLR2)
129
Compare/Capture Enable Register (TIM2_CCER)
130
Counter for General-Purpose Timer (TIM2_CNT)
130
Counting Clock Prescaler (TIM2_PSC)
131
Auto-Reload Value Register (TIM2_ATRLR)
131
Compare/Capture Registers
131
DMA Control Register (TIM2_DMACFGR)
132
DMA Address Register for Continuous Mode (TIM2_DMAADR)
132
Universal Synchronous Asynchronous Receiver Transmitter (USART)
133
Baud Rate Generator
134
Synchronous Mode
134
Single-Wire Half-Duplex Mode
135
Smart Card
135
Irda
136
Dma
136
Interruptions
136
(Un)Occurrence of Parity Error Diagram
136
USART-Related Registers List
137
USART Status Register (USART_STATR)
137
USART Data Register (USART_DATAR)
139
USART Control Register 1 (USART_CTLR1)
140
USART Control Register 2 (USART_CTLR2)
141
USART Control Register 3 (USART_CTLR3)
142
USART Guard Time and Prescaler Register (USART_GPR)
143
Inter-Integrated Circuit (I2C) Interface
144
I2C Timing Diagram
144
Master Mode
145
Slave Mode
146
Error Conditions
147
Bus Error (Berr)/Acknowledge Failure (AF)
147
Arbitration Lost (ARLO)
147
Overrun/Underrun Error (OVR)
147
Clock Extension
148
Smbus
148
Transmission Using DMA
149
Reception Using DMA
149
Packet Error Checking
150
I2C-Related Registers List
150
I2C Control Register
150
I2C Own Address Register
152
I2C Data Register (I2C_DATAR)
153
I2C Status Register
153
I2C Clock Register (I2C1_CKCFGR)
156
Serial Peripheral Interface (SPI)
157
SPI Structure Block Diagram
157
SPI Mode
158
Simplex Mode
159
Crc
159
Errors
160
SPI-Related Registers List
160
Master Mode Fault (MODF)
160
SPI Control Register 2 (SPI1_CTLR2)
161
SPI Status Register (SPI1_STATR)
162
SPI Status Register (SPI1_DATAR)
163
SPI1 Polynomial Register (SPI1_RCRCR)
163
SPI1 Receive CRC Register (SPI1_TCRCR)
163
SPI1 Transmit CRC Register (SPI1_TCRCR)
164
SPI High-Speed Control Register (SPI1_HSCR)
164
Electronic Signature (ESIG)
165
ESIG-Related Registers List
165
Flash Capacity Register (ESIG_FLACAP)
165
UID Register
165
Flash Memory and User Option Bytes
167
Flash Memory Organization
167
Flash Memory Programming and Security
167
Security - Prevent Illegal Access (Read, Write, Erase)
167
Control Register (FLASH_ACTLR)
168
FPEC Key Register (FLASH_KEYR)
168
OBKEY Register (FLASH_OBTKEYR)
168
Configuration Register (FLASH_ CTLR)
169
Address Register (FLASH_ ADDR)
170
Select Word Register (FLASH_OBR)
171
Write Protect Register (FLASH_WPR)
171
Flash Memory Operation Flow
172
Unlocking the Flash Memory
172
Extended Key Register (FLASH_MODEKEYR)
172
BOOT Key Register (FLASH_BOOT_MODEKEYP)
172
Main Memory Standard Programming
173
Main Memory Standard Erase
173
FLASH Page Erase
174
FLASH Whole Chip Erase
174
Fast Programming Mode Unlocking
175
Main Memory Fast Programming
175
Main Memory Fast Erase
175
User-Selected Words
176
User-Selected Word Unlocking
177
User-Selected Word Programming
177
User-Selected Word Erasure
178
Unprotecting Reads
178
Extended Configuration
179
Configuring the Extended Control Register (EXTEND_CTR)
179
Debug Support (DBG)
181
Debug MCU Configuration Register (DBGMCU_CR)
181

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WCH CH32V003 Series Reference Manual (182 pages)

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