Reset And Clock Control (Rcc); Power Reset; System Reset - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual
Chapter 3 Reset and Clock Control (RCC)
The controller provides different forms of resets and configurable clock tree structures based on the division
of power areas and peripheral power management considerations in the application. This section describes the
scope of each clock in the system.
3.1 Main features
l Multiple reset forms
l Multiple clock sources, bus clock management
l Built-in external crystal oscillation monitoring and clock security system
l Independent management of each peripheral clock: reset, on, off
l Supports internal clock output
3.2 Reset
The controller provides 2 forms of reset: power Reset and system Reset.

3.2.1 Power Reset

When a power Reset occurs, it will reset all registers.
A power Reset is generated when the following event occurs:
l
Power-up/power-down reset (POR/PDR)

3.2.2 System Reset

When a system Reset occurs, it will reset the reset flag in addition to the control/status register
RCC_RSTSCKR and all the registers. The source of the reset event is identified by looking at the reset status
flag bit in the RCC_RSTSCKR register.
A system Reset is generated when one of the following events occurs:
l
Low signal on NRST pin (external reset)
l Window watchdog count termination (WWDG reset)
l Independent watchdog count termination (IWDG reset)
l
Software reset (SW reset)
l
Low-power management reset
Window/Independent Watchdog Reset: Generated by the window/independent watchdog peripheral timer
count cycle overflow trigger, see its corresponding section for detailed description.
Software reset: The CH32V003 product resets the system via RESETSYS location 1 of the interrupt
configuration register PFIC_CFGR in the programmable interrupt controller PFIC or SYSRESET location 1
of the configuration register PFIC_SCTLR to reset the system cabinet, refer to the corresponding chapter for
details.
Low-Power management reset: Standby mode reset will be enabled by placing the STANDBY_RST location
01 in the user select byte. This will perform a system Reset instead of entering Standby mode after the process
of entering Standby mode is executed.
V1.3 11
http://wch.cn