Brake Signal; Single Pulse Mode; Complementary Outputs And Deadband - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual
output pin) and can output two complementary signals (OCx and OCxN). OCx and OCxN can be
independently set for polarity via the CCxP and CCxNP bits, independently set for output enable via CCxE
and CCxNE, and independently set for output enable via the MOE, OIS, OISN, OSSI, and OSSR bits for
deadband and other controls. Enabling the OCx and OCxN outputs simultaneously will insert a deadband, and
each channel has a 10-bit deadband generator. OCx and OCxN are generated by the OCxREF association. If
both OCx and OCxN are high active, then OCx is the same as OCxREF except that the rising edge of OCx is
equivalent to OCxREF with a delay, and OCxN is the opposite of OCxREF in that its rising edge will have a
delay relative to the falling edge of the reference signal. If the delay is greater than the effective output width,
the corresponding pulse will not be generated.
The relationship between OCx and OCxN and OCxREF is illustrated in Figure 10-4, which shows the dead
zone.

10.3.7 Brake signal

When the brake signal is generated, the output enable signal and invalid level are modified according to the
MOE, OIS, OISN, OSSI, and OSSR bits. However, OCx and OCxN will not be at the active level at any time.
The source of the brake event can come from the brake input pin or it can be a clock failure event which is
generated by the CSS (Clock Safety System).
After system reset, the brake function is disabled by default (MOE bit is low), and setting the BKE bit enables
the brake function. The polarity of the input brake signal can be set by setting BKP, and the BKE and BKP
signals can be written at the same time, and there is a delay of one APB clock before the actual writing, so you
need to wait for one APB cycle to read the written value correctly.
At the presence of the selected level on the brake pin the system will generate the following actions.
1) The MOE bit is cleared asynchronously, setting the output to an invalid, idle or reset state, depending on
the setting of the SOOI bit.
2) After the MOE has been cleared, each output channel outputs a level determined by OISx.
3) When using complementary outputs: the outputs are placed in a null state, depending on the polarity.
4) If the BIE is set, an interrupt is generated when the BIF is set; if the BDE bit is set, a DMA request is
generated.
5) If the AOE is set, the MOE bit is automatically set at the next update event UEV.

10.3.8 Single pulse mode

Single pulse mode can be used to allow the microcontroller to respond to a specific event by causing it to
generate a pulse after a delay, with the delay and width of the pulse programmable. Placing the OPM bit allows
the core counter to stop when the next update event UEV is generated (counter flips to 0).
As shown in Figure 10-5, a positive pulse of length Tpulse needs to be generated on OC1 after a delay Tdelay
at the beginning of a rising edge detected on the TI2 input pin.
V1.3
Figure 10-4 Complementary outputs and deadband
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