WCH CH32V003 Series Reference Manual page 127

CH32V003 Reference Manual
the channel in input mode.
15 14 13 12
OC2CE OC2M[2:0]
IC2F[3:0]
Comparison mode (pin direction is output).
Bit Name
15 OC2CE
[14:12] OC2M
11 OC2PE
V1.3
11 10 9
OC2PE OC2FE
CC2S[1:0]
IC2PSC[1:0]
Access
Compare capture channel 2 clear enable bit.
1: Clear the OC2REF bit zero once the ETRF input is
RW
detected high.
0: OC2REF is not affected by the ETRF input.
Compare the Capture Channel 2 mode setting field.
The 3 bits define the action of the output reference
signal OC2REF, which determines the values of OC2,
OC2N. OC2REF is active high, while the active levels
of OC2 and OC2N depend on the CC2P, CC2NP bits.
000: Freeze. Comparison of the value of the capture
register with the value of the comparison between the
core counters does not work for OC1REF.
001: force to set to valid level. Forcing OC1REF high
when the core counter has the same value as the
comparison capture register 1.
010: Force to set to invalid level. Forcing OC1REF low
when the value of the core counter is the same as the
comparison capture register 1.
011: Flip. Flips the level of OC1REF when the core
counter is the same as the value of compare capture
register 1.
100: Forced to invalid level. Forces OC1REF to low.
101: Force to valid level. Force OC1REF to high.
RW 110: PWM mode 1: When counting up, channel 1 is
invalid level once the core counter is greater than the
value of the compare capture register, otherwise it is
valid level; when counting down, channel 1 is valid
level once the core counter is greater than the value of
the compare capture register, otherwise it is invalid
level.
111: PWM mode 2: When counting up, channel 1 is
valid level once the core counter is greater than the
value of the compare capture register, otherwise it is
invalid level; when counting down, channel 1 is invalid
level once the core counter is greater than the value of
the compare capture register, otherwise it is valid level
(OC1REF=1).
Note: This bit cannot be modified once the LOCK level
is set to 3 and CC1S=00b. In PWM mode 1 or PWM
mode 2, the OC1REF level is changed only when the
comparison result is changed or when switching from
freeze mode to PWM mode in the output comparison
mode.
Compare Capture Register 2 preload enable bit.
1: turn on the preload function of the compare capture
register, the read and write operations operate only on
the preload register, and the preload value of the
RW
compare capture register 1 is loaded into the current
shadow register when the update event comes.
0: Disable the preload function of compare capture
register 2. The compare capture register 2 can be
8 7 6 5
OC1CE OC1M[2:0]
IC1F[3:0]
Description
127
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4 3 2 1
OC1PE OC1FE
CC1S[1:0]
IC1PSC[1:0]
Reset
value
0
0
0
0