Power Control (Pwr); Power Management; Power-On Reset And Power-Down Reset; Programmable Voltage Detector - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual
2.1 Overview
The system operating voltage V
power supply required by the core.

2.2 Power management

2.2.1 Power-on reset and power-down reset

The system has an internal power-on reset POR and a power-down reset PDR circuit. When the chip supply
voltage V falls below the corresponding threshold voltage, the system is reset by the relevant circuit, and no
DD
additional external reset circuit is required. Please refer to the corresponding datasheet for the parameters of
the power-on threshold voltage V
Figure 2-2 Schematic diagram of the operation of POR and PDR
V
DD(A)
Reset signal

2.2.2 Programmable voltage detector

The programmable voltage monitor, PVD, is mainly used to monitor the change of the main power supply of
the system and compare it with the threshold voltage set by PLS[2:0] of the power control register PWR_CTLR,
V1.3
Chapter 2 Power Control (PWR)
ranges from 2.7 to 5.5V, and the built-in voltage regulator provides the 1.5V
DD
Figure 2-1 Block diagram of power supply structure
V power supply domain
DD
AD converters
reset module
I/O circuit
V
DD
Standby circuit
(Wake-up logic,
V
SS
Voltage regulator
and the power-down threshold voltage V
POR
V
POR
40-110mV
Reset lag time
t
RSTTEMPO
0
1.5V
power supply
domain
PLL
CPU cores
memory
Built-in
IWDG)
digital
peripherals
Hysteresis
1
5
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.
PDR
V
PDR
0