Pfic Interrupt Pending Clear Register 2 (Pfic_Ipsr2); Pfic Interrupt Activation Status Register 1 (Pfic_Iactr1) - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual
15 Reserved
14 PENDRESET14
13 Reserved
12 PENDRESET12
[11:4] Reserved
[3:2] PENDRESET2_3
[1:0] Reserved

6.5.2.18 PFIC interrupt pending clear register 2 (PFIC_IPSR2)

Offset address: 0x284
31 30 29 28
15 14 13 12
Bit
[31:7] Reserved
[6:0] PENDRESET32_38

6.5.2.19 PFIC interrupt activation status register 1 (PFIC_IACTR1)

Offset address: 0x300
31 30 29 28
15 14 13 12
Reser IACTS1 Reser IACTS1
ved 4 ved
Bit Name
[31:16] IACTS16_31
15 Reserved
14 IACTS14
13 Reserved
12 IACTS12
[11:4] Reserved
V1.3
RO Reserved
14# Interrupt hang clear.
1: The current numbered interrupt clears
WO
the pending state.
0: No effect.
RO Reserved
12# Interrupt hang clear.
1: The current numbered interrupt clears
WO
the pending state.
0: No effect.
RO Reserved
2#-3# interrupt hang clear.
1: The current numbered interrupt clears
WO
the pending state.
0: No effect.
RO Reserved
27 26 25
11 10 9
Reserved
Name Access
RO
WO
27 26 25
IACTS [31:16]
11 10 9
2
Access
16#-31# Interrupt execution status.
RO 1: current number interruption in execution.
0: The current number interrupt is not executed.
RO Reserved
14# Interrupt execution status.
RO 1: current number interruption in execution.
0: The current number interrupt is not executed.
RO Reserved
12# Interrupt execution status.
RO 1: current number interruption in execution.
0: The current number interrupt is not executed.
RO Reserved
24 23 22 21
Reserved
8 7 6 5
Description
Reserved
32#-38# interrupt hang clear.
1: The current numbered interrupt clears
the pending state.
0: No effect.
24 23 22 21
8 7 6 5
Reserved
Description
44
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0
0
0
0
0
0
0
20 19 18 17
4 3 2
PENDRESET[38:32]
Reset value
20 19 18 17
4 3 2
IACTS IACTS
Reserved
3 2
Reset value
16
1 0
0
0
16
1 0
0
0
0
0
0
0