Block Diagram Of Advanced-Control Timer Structure - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual
Figure 10-1 Block diagram of advanced-control timer structure
CK_TIM18 from RCC
ETR
Polarity selection,
Edge detector and Prescaler
ITR0
ITR1
ITR2
ITR3
TI1
Input filter &
Edge detector
TI2
Input filter &
Edge detector
TI3
Input filter &
Edge detector
TI4
Input filter &
Edge detector
BRK
Polarity selection
Clock failure event from clock controller
CSS (Clock Security System)
V1.3
Internal clock(CK_INT)
ETRF
ETRP
Input filter
TGI
TRGI
ITR
TRC
TIF_ED
TI1FP1
TI2FP2
CK_PSC
(prescaler)
TI1FP1 TI1FP1
IC1
Prescaler
TI1FP2
TRC
TI2FP1
IC2
Prescaler
TI2FP2
TRC
TI3FP3
IC3
Prescaler
TI3FP4
TRC
TI4FP3
IC4
Prescaler
TI4FP4
TRC
Trigger
controller
TRGO
Slave mode
controller
Reset,
Enable,
Up/Down,
Count
Encoder
interface
AutoReload
U
Register
CK_CNT
PSC CNT
(counter)
CC4I
IC1PS IC1PS
Capture/Compare
1 Register
U
CC3I
IC2PS
Capture/Compare
2 Register
U
CC2I
IC3PS
Capture/Compare
3 Register
U
CC1I
IC4PS
Capture/Compare
4 Register
U
BI
87
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To other timers
To DAC and ADC
UI
REP Register
U
Repetition counter
DTG[7:0]registers
CC4I
OC1REF
CC3I
OC2REF
OC2N
CC2I
OC3
OC3REF
CC1I
OC4REF
OC4