Select Word Register (Flash_Obr); Write Protect Register (Flash_Wpr) - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual
15 14 13 12
Bit Name
[31:0] ADDR

16.3.7 Select word register (FLASH_OBR)

Offset address: 0x14
31 30 29 28
Reserved
15 14 13 12
DATA0
Bit Name
[31:26] Reserved
[25:18] DATA1
[17:10] DATA0
[9:8]
7
[6:5] CFGRSTT
STANDY_
4
3
2 IWDG_SW
1 RDPRT
0 OBERR
Note: USER and RDPRT are loaded from the user-selected word area after a system reset.

16.3.8 Write protect register (FLASH_WPR)

Offset address: 0x20
31 30 29 28
15 14 13 12
Bit Name
[31:0] WPR
V1.3
11 10 9
ADDR[15:0]
Access
The flash memory address, when programming, is
the programmed address, and when erasing, is the
WO start address of the erase.
When the BSY bit in FLASH_SR register is '1',
this register cannot be written.
27 26 25
11 10 9
2'b11
Access
RO
Reserved RO
RO
RO
RST
Reserved RO
RO
RO
RO
27 26 25
WPR[31:16]
11 10 9
Access
Flash memory write protect state.
RO 1: Write protection failure.
0: Write protection is valid.
8 7 6 5
Description
24 23 22 21
DATA1
8 7 6 5
Reser
CFGRSTT
ved
Description
Reserved
Data byte 1
Data byte 0
2'b11
Reserved
Configuration word reset delay time
System reset control in Standby mode.
Reserved
Independent Watchdog
hardware enable bit.
Read protection status.
1: Indicates that the flash memory is
currently read protected.
Wrong choice of words.
1: Indicates that the selection word and its
inverse code do not match.
24 23 22 21
8 7 6 5
WPR[15:0]
Description
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4 3 2 1
Reset value
0
20 19 18 17
DATA0
4 3 2 1
STAN IW
STOP RDP
DY DG
RST RT
RST SW
Reset value
0
X
X
X
X
X
X
(IWDG)
1
1
0
20 19 18 17
4 3 2 1
Reset value
X
0
16
0
OBE
RR
16
0