WCH CH32V003 Series Reference Manual page 99

CH32V003 Reference Manual
Bit Name
15 ETP
14 ECE
[13:12] ETPS
[11:8] ETF
7 MSM
[6:4] TS
V1.3
Access
ETR trigger polarity selection, this bit selects whether
to input ETR directly or to input the inverse of ETR.
RO
1: Invert ETR, low or falling edge active;
0: ETR, active high or rising edge.
External clock mode 2 enable selection.
1: Enables external clock mode 2.
0: Disable external clock mode 2.
Note 1: Slave mode can be used simultaneously with
external clock mode 2: reset mode, gated mode and
RW
trigger mode; however, TRGI cannot be connected to
ETRF in this case (TS bit cannot be '111').
Note 2: When both external clock mode 1 and external
clock mode 2 are enabled, the external clock input is
ETRF.
The external trigger signal (ETRP) divides the
frequency of this signal, which cannot exceed a
maximum of 1/4 of the TIMxCLK frequency, and can
be downconverted through this domain.
RW
00: Prescaler off.
01: ETRP frequency divided by 2.
10: ETRP frequency divided by 4.
11: ETRP frequency divided by 8.
Externally triggered filtering, in fact, the digital filter is
an event counter, which uses a certain sampling
frequency to record up to N events and then produces a
jump in the output.
0001: sampling frequency Fsampling=Fck_int, N=2.
0010: sampling frequency Fsampling=Fck_int, N=4.
0011: Sampling frequency Fsampling=Fck_int, N=8.
0100: sampling frequency Fsampling = Fdts/2, N = 6.
0101: sampling frequency Fsampling = Fdts/2, N = 8.
RW 0110: sampling frequency Fsampling = Fdts/4, N = 6.
0111: sampling frequency Fsampling = Fdts/4, N = 8.
1000: sampling frequency Fsampling = Fdts/8, N = 6.
1001: sampling frequency Fsampling = Fdts/8, N = 8.
1010: sampling frequency Fsampling = Fdts/16, N = 5.
1011: sampling frequency Fsampling = Fdts/16, N = 6.
1100: sampling frequency Fsampling = Fdts/16, N = 8.
1101: sampling frequency Fsampling = Fdts/32, N = 5.
1110: sampling frequency Fsampling = Fdts/32, N = 6.
1111: Sampling frequency Fsampling=Fdts/32, N=8.
Master/slave mode selection.
1: The event on the trigger input (TRGI) is delayed to
allow perfect synchronization between the current timer
RW (via TRGO) and its slave timer. This is useful when the
synchronization of several timers to a single external
event is required.
0: Does not function.
Trigger selection field, these 3 bits select the trigger
input source used to synchronize the counter.
000: Internal trigger 0 (ITR0).
RW 001: Internal trigger 1 (ITR1).
010: Internal trigger 2 (ITR2).
011: Internal trigger 3 (ITR3).
100: Edge detector of TI1 (TI1F_ED).
99
Description
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Reset
value
0
0
0
0
0
0