WCH CH32V003 Series Reference Manual page 3

CH32V003 Reference Manual
on this bus.
l The data bus (D-Code) connects the core to the FLASH data interface for constant loading and debugging.
l The system bus connects the core to the bus matrix and is used to coordinate accesses to the core, DMA,
SRAM and peripherals.
l The DMA bus is responsible for the DMA of the AHB master interface connected to the bus matrix, which
is accessed by FLASH data, SRAM and peripherals.
l The BusMatrix is responsible for the access coordination between the system bus, data bus, DMA bus,
SRAM and AHB/APB bridge.
l The AHB bridge provides full synchronous connections between the AHB bus and the two APB buses.
With different peripherals hooked up under different APB buses, different bus clocks can be configured
to optimize performance according to actual needs.
V1.3 2
http://wch.cn