Error Conditions; Bus Error (Berr)/Acknowledge Failure (Af); Arbitration Lost (Arlo); Overrun/Underrun Error (Ovr) - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual
7-bit address), the I2C module will go to transmitter mode and the TRA bit will indicate whether it is currently
receiver or transmitter mode.
In transmit mode, after clearing the ADDR bit, the I2C module sends bytes from the data register to the SDA
line via a shift register. After an answer ACK is received, the TxE bit is set and an interrupt is generated if
ITEVTEN and ITBUFEN are set. If TxE is set but no new data is written to the data register before the end of
the next data send, the BTF bit will be set. SCL will remain low until the BTF is cleared. Reading status register
1 (R16_I2Cx_STAR1) and then writing data to the data register will clear the BTF bit.
In receive mode, after ADDR is cleared, the I2C module stores the data on SDA into the data register via the
shift register. After each byte is received, the I2C module sets an ACK bit and sets the RxNE bit, and generates
an interrupt if ITEVTEN and ITBUFEN are set. If RxNE is set and the old data is not read before the new data
is received, then BTF is set. SCL will remain low until the BTF bit is cleared. Reading status register 1
(R16_I2Cx_STAR1) and reading the data in the data register will clear the BTF bit.
When the I2C module detects a stop event, it will set the STOPF bit and generate an interrupt if the ITEVFEN
bit is set. The user needs to read the status register(R16_I2Cx_STAR1) and then write the control register (e.g.
reset control word SWRST) to clear it.

13.5 Error conditions

13.5.1 Bus error (BERR)
A bus error will be generated when the I2C module detects an external start or stop event during address or
data transfer. When a bus error is generated, the BERR bit is set and an interrupt is generated if ITERREN is
set. In slave mode, the data is discarded and the hardware releases the bus. If it is a start signal, the hardware
assumes it is a restart signal and starts waiting for an address or stop signal; if it is a stop signal, it operates
ahead of normal stop conditions. In master mode, the hardware does not release the bus while not affecting
the current transfer, and it is up to the user code to decide whether to abort the transfer.
13.5.2 Acknowledge failure (AF)
An answer error will be generated when the I2C module detects a byte and then no answer. When an answer
error is generated: AF will be set and an interrupt will be generated if ITERREN is set; when an AF error is
encountered, the hardware must release the bus if the I2C module is working in slave mode and the software
must generate a stop event if it is in master mode.

13.5.3 Arbitration lost (ARLO)

An arbitration lost error is generated when the I2C module detects an arbitration lost. When an arbitration loss
error is generated: the ARLO bit is set and an interrupt is generated if ITERREN is set; the I2C module switches
to slave mode and no longer responds to transfers initiated against its slave address unless a new start event is
initiated by the host; the hardware releases the bus.

13.5.4 Overrun/underrun error (OVR)

Overrun error
l
In Slave mode, if the clock extension is disabled and the I2C module is receiving data, an overrun error will
occur if a byte of data has been received but the last received data has not been read out. When an overrun
error occurs, the last received byte will be discarded and the sender should retransmit the last sent byte.
Underrun error
l
In Slave mode, if the clock is forbidden to extend and the I2C module is sending data, an underrun error will
occur if new data has not been written to the data register before the next byte of the clock comes. In case of
an underrun error, the data in the previous data register will be sent twice, and if an underrun error occurs, then
the receiver should discard the data received repeatedly. In order not to generate an underrun error, the I2C
module should write the data to the data register before the first rising edge of the next byte.
V1.3 147
http://wch.cn