Low-Power Modes - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual
and with the external interrupt register (EXTI) setting, it can generate relevant interrupts to notify the system
in time for pre-power down operations such as data saving.
The specific configuration is as follows.
1) Set the PLS[2:0] field of the PWR_CTLR register to select the voltage threshold to be monitored.
2) Optional interrupt handling. the PVD function internally connects to the rising/falling edge trigger setting
of line 8 of the EXTI module, turns on this interrupt (configures EXTI), and generates a PVD interrupt
when VDD drops below the PVD threshold or rises above the PVD threshold.
3) Set the PVDE bit of PWR_CTLR register to enable the PVD function.
4) Read the PVD0 bit of PWR_CSR status register to obtain the current system main power and PLS[2:0]
setting threshold relationship, and perform the corresponding soft processing.
PVD
output

2.3 Low-power modes

After a system reset, the microcontroller is in a normal operating state (run mode), where system power can
be saved by reducing the system main frequency or turning off the unused peripheral clock or reducing the
operating peripheral clock. If the system does not need to work, you can set the system to enter low-power
mode and let the system jump out of this state by specific events.
Microcontrollers currently offer 2 low-power modes, divided in terms of operating differences between
processors, peripherals, voltage regulators, etc.
l Sleep mode: The core stops running and all peripherals (including core private peripherals) are still
running.
l
Standby mode: Stop all clocks, wake up and switch the clock to HSI.
Mode Entry
WFI
Sleep
WFE
Set SLEEPDEEP
to 1
Standby
Set PDDS to 1
WFI or WFE
Note: The SLEEPDEEP bit belongs to the core private peripheral control bit, CH32V003 product reference
PFIC_SCTLR register.
V1.3
Figure 2-3 Schematic diagram of PVD operation
V
DD(A)
1
Table 2-1 Low-power Mode List
Wake-up source
Any interrupt
Wake-up event
AWU event, NRST pin reset,
IWDG reset.
Note: Any event can also wake
up the system, but the system
does not reset after waking up.
PVD
valve value
0
Effect on clock
Core clock OFF,
no effect on other
clocks
HSE, HSI, PLL
and peripheral
clock OFF
6
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Approx.
200mV
hysteresis
1
Voltage
regulator
ON
OFF