Pfic Interrupt Enable Status Register 2; Pfic Interrupt Pending Status Register 1 - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual
[3:2] INTENSTA2_3
[1:0] Reserved
6.5.2.2 PFIC interrupt enable status register 2 (PFIC_ISR2)
Offset address: 0x04
31 30 29 28
15 14 13 12
Bit Name
[31:7] Reserved
[6:0] INTENSTA32_38
6.5.2.3 PFIC interrupt pending status register 1 (PFIC_IPR1)
Offset address: 0x20
31 30 29 28
15 14 13 12
PEN PEN
Reser Reser
DST DST
ved ved
A14 A12
Bit Name
[31:16] PENDSTA16_31
15 Reserved
14 PENDSTA14
13 Reserved
12 PENDSTA12
[11:4] Reserved
[3:2] PENDSTA2_3
[1:0] Reserved
V1.3
2#-3# interrupt current enable state.
1: The current numbered interrupt is
RO enabled.
0: The current numbered interrupt is not
enabled.
RO Reserved
27 26 25
11 10 9
Reserved
Access
RO Reserved
32#-38# Interrupt current enable state.
1: The current numbered interrupt is
RO enabled.
0: The current numbered interrupt is not
enabled.
27 26 25
PENDSTA[31:16]
11 10 9
Access
1216#-31# interrupt the current pending
status.
RO
1: The current number break is pending.
0: The current number break is not pending.
RO Reserved
14# Interrupt the current pending state.
1: The current number break is pending.
0: The current number break is not pending.
RO Reserved
12# Interrupt the current pending state.
1: The current number break is pending.
0: The current number break is not pending.
RO Reserved
2#-3# interrupt the current pending state.
RO 1: The current number break is pending.
0: The current number break is not pending.
RO Reserved
24 23 22 21
Reserved
8 7 6 5
Description
24 23 22 21
8 7 6 5
Reserved
Description
38
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0
0
20 19 18 17
4 3 2 1
INTENSTA[6:0]
Reset value
0
0
20 19 18 17
4 3 2 1
PEN PEN
DST DST Reserved
A3 A2
Reset value
0
0
0
0
0
0
0
0
16
0
16
0