Wwdg-Related Registers List; Control Register (Wwdg_Ctlr); Configuration Register (Wwdg_Cfgr) - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual
5.2.2 Debug mode
When the system enters Debug mode, the counter of WWDG can be configured by the debug module register
to continue or stop.
5.3 Register description
Name
R16_WWDG_CTLR
R16_WWDG_CFGR
R16_WWDG_STATR

5.3.1 Control register (WWDG_CTLR)

Offset address: 0x00
15 14 13 12
Reserved
Bit Name
[15:8] Reserved
7 WDGA
[6:0] T

5.3.2 Configuration register (WWDG_CFGR)

Offset address: 0x04
15 14 13 12
Reserved
Bit Name
[15:10] Reserved
9 EWI
[8:7] WDGTB
[6:0] W
V1.3
Table 5-1 WWDG-related registers list
Access address
0x40002C00 Control register
0x40002C04 Configuration Register
0x40002C08 Status Register
11 10 9 8
Access
RO Reserved
Window watchdog reset enable bit.
1: Turn on the watchdog function (which generates
a reset signal).
RW1
0: Disable the watchdog function. Software write
1 is on, but only allows hardware to clear 0 after
reset.
The 7-bit self-decrement counter decrements by 1
every 4096*2
RW
reset is generated when the counter decrements
from 0x40 to 0x3F, i.e., when T6 jumps to 0.
11 10 9 8
WDGTB[1:0
EWI
Access
RO Reserved
Early wakeup interrupt enable bit.
If this position is 1, an interrupt is generated when
RW1
the counter value reaches 0x40. This bit can only
be invited to 0 by hardware after a reset.
Window watchdog clock division selection.
00: Divided by 1, counting time base =
PCLK1/4096.
01: Divided by 2, counting time base =
RW PCLK1/4096/2.
10: Divided by 4, counting time base =
PCLK1/4096/4.
11: Divided by 8, counting time base =
PCLK1/4096/8.
Window watchdog 7-bit window value. Used to
RW
compare with the counter value. The feed dog
Description
7 6 5
WDG
A
Description
WDGTB PCLK1 cycles. A watchdog
7 6 5
]
Description
30
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Reset value
0x007F
0x007F
0x0000
4 3 2 1
T[6:0]
Reset value
0
0
7Fh
4 3 2 1
W[6:0]
Reset value
0
0
0
7Fh
0
0