Usart Control Register 1 (Usart_Ctlr1) - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual

12.10.4 USART Control register 1 (USART_CTLR1)

Offset address: 0x0C
31 30 29 28
15 14 13 12
Reserved UE M
Bit Name
[31:14] Reserved
13 UE
12 M
11 WAKE
10 PCE
9 PS
8 PEIE
7 TXEIE
6 TCIE
5 RXNEIE
4 IDLEIE
3 TE
2 RE
1 RWU
0 SBK
V1.3
27 26 25 24
Reserved
11 10 9 8
WAK
PCE PS PEIE
E
Access
RO Reserved
USART enable bit. When this bit is set, both the
RW USART divider and the output stop working after
the current byte transfer is completed.
Word long bit.
RW
1: 9 data bits; 0: 8 data bits.
Wake-up bit. This bit determines the method of
RW waking up the USART.
1: Address marker; 0: Bus idle.
The parity bit is enabled. For the receiver, it is the
parity check of the data; for the sender, it is the
RW insertion of the parity bit. Once this bit is set, the
parity bit enable will take effect only after the
current byte transmission is completed.
Parity selection. 0 means even parity, 1 means odd
parity. When this bit is set, the parity bit enable
RW
will take effect only after the current byte
transmission is completed.
Parity check interrupt enable bit. This bit indicates
RW
that parity check error interrupts are allowed.
TXE interrupt enable. This bit indicates that a
RW
TXE interrupt is allowed to be generated.
Transmit completion interrupt enable. This bit
RW indicates that the transmit completion interrupt is
allowed to be generated.
RXNE interrupt enable. This bit indicates that a
RW
RXNE interrupt is allowed to be generated.
IDLE interrupt enable. This bit allows IDLE
RW
interrupt to be generated.
Transmitter enable. Setting this bit will enable the
RW
transmitter.
Receiver enable. Setting this bit enables the
RW receiver, which starts detecting the start bit on the
RX pin.
Receiver wakeup. This bit determines whether to
place the USART in silent mode.
1: The receiver is in silent mode.
0: The receiver is in normal operation mode.
Note 1: Before setting the RWU bit, the USART
RW
needs to receive a data byte first, otherwise it
cannot be woken up by bus idle in silent mode.
Note 2: When configured as address mark wake-
up, the RWU bit cannot be modified by software
when RXNE is set.
Send break bit.
RW Set this bit to send break character. It is reset by
hardware on the stop bit of the break frame.
23 22 21
7 6 5
TXEI RXNE IDLEI
TCIE
E IE
Description
140
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20 19 18 17
4 3 2 1
TE RE RWU SBK
E
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
0