Slave Mode - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual
sent is the address byte, the first 7 bits represent the address of the target slave device, the 8
the direction of the subsequent message, 0 means the master device writes data to the slave device, 1 means
the master device reads information to the slave device. In 10-bit address mode, as shown in Figure 13-3, in
the send address phase, the first byte is 11110xx0, xx is the highest 2 bits of the 10-bit address, and the second
byte is the lower 8 bits of the 10-bit address. If subsequently enter the master device transmit mode, continue
to send data; if subsequently ready to enter the master device receive mode, you need to re-send a start
condition, follow to send a byte as 11110xx1, and then enter the master device receive mode.
Figure 13-3 Schematic diagram of host sending and receiving data at 10-bit address
S
S 1 1 1 1 0 X X
(The upper 2 bits
of the address)
In transmit mode, the master device's internal shift register sends data from the data register to the SDA line.
When the master device receives an ACK, TxE in status register 1 (R16_I2Cx_STAR1) is set, and an interrupt
is generated if ITEVTEN and ITBUFEN are set. Writing data to the data register will clear the TxE bit. If the
TxE bit is set and no new data was written to the data register before the last data was sent, then the BTF bit
will be set and SCL will remain low until it is cleared, and writing data to the data register after reading
R16_I2Cx_STAR1 will clear the BTF bit. While in receive mode, the I2C module will receive data from the
SDA line and write it into the data register via the shift register. After each byte, if the ACK bit is set, the I2C
module will send an answer low and the RxNE bit will be set, and an interrupt will be generated if ITEVTEN
and ITBUFEN are set. If RxNE is set and the original data is not read before the new data is received, the BTF
bit will be set and SCL will remain low until the BTF is cleared. Reading R16_I2Cx_STAR1 and then reading
the data register will clear the BTF bit.
The master device will initiate an end event, i.e. set the STOP bit, when it finishes sending data. In receive
mode, the master device needs to NAK at the answer position of the last data bit. note that after generating
NAK, the I2C module will switch to slave mode.

13.4 Slave mode

When in slave mode, the I2C module recognizes its own address and the broadcast call address. The software
can control whether the recognition of the broadcast call address is enabled or disabled. Once a start event is
detected, the I2C module compares the SDA data through the shift register with its own address (number of
bits depends on ENDUAL and ADDMODE) or the broadcast address (when ENGC is set), if there is a
mismatch it will be ignored until a new start event is generated. If it matches the header sequence, an ACK
signal is generated and the address of the second byte is waited for; if the address of the second byte also
matches or the full segment address matches in the case of a 7- bit address, then: first an ACK answer is
generated; the ADDR bit is set, and if the ITEVTEN bit is already set, then a corresponding interrupt is also
generated; if the dual address mode is used (ENDUAL bit is set), the DUALF bit also needs to be read to
determine which address the host is evoking.
The slave mode is receive mode by default. In case the last bit of the received header sequence is 1, or the last
bit of the 7-bit address is 1 (depending on whether the header sequence is received for the first time or a normal
V1.3
Transmitter
1 1 1 1 0 X X 0 A
(The upper 2 bits
(Write)
of the address)
0 A Address 7- 0 A
The lower 8 bits of
(Write)
the address
Address 7- 0 A DATA
The lower 8 bits of
the address
Receiver
S 1 1 1 1 0 X X
(Write)
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bit determines
A DATA A P
1 A DATA A DATA A P