Clock Extension; Smbus - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual

13.6 Clock extension

If clock extension is disabled, then there is a possibility of overrun/underrun errors. However, if clock
extension is enabled:
l In transmit mode, if TxE is set and BTF is set, SCL will always be low, always waiting for the user to
read the status register and write the data to be sent to the data register.
l
In receive mode, if RxNE is set and BTF is set, SCL will remain low after data is received until the user
reads the status register and reads the data register.
It can be seen that enabling clock extension can avoid overrun/underrun errors.

13.7 SMBus

SMBus is also a two-wire interface, which is generally used between system and power management. SMBus
and I2C have many similarities, for example, SMBus uses the same 7-bit address mode as I2C, and the
following are common to SMBus and I2C.
1) Master-slave communication mode, where the host provides the clock and supports multiple masters and
slaves.
2) Two-wire communication architecture, with an optional warning line for SMBus.
3) Both support 7-bit address format.
There are also differences between SMBus and I2C.
1) I2C supports speeds up to 400 KHz, while SMBus supports up to 100 KHz, and SMBus has a minimum
speed limit of 10 KHz.
2) A timeout will be reported when the SMBus clock is low for more than 35mS, but there is no such limit
for I2C.
3) SMBus has a fixed logic level, while I2C does not, depending on VDD.
4) SMBus has a bus protocol, while I2C does not.
SMBus also includes device identification, address resolution protocols, unique device identifiers, SMBus
reminders and various bus protocols as described in the SMBus specification version 2.0. When using SMBus,
only the SMBus bit of the control register needs to be set, and the SMBTYPE bit and ENAARP bit need to be
configured as needed.
13.8 Interruptions
Each I2C module has two interrupt vectors, event interrupts and error interrupts. Both interrupts support the
interrupt sources in Figure 13-4.
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