Spi Status Register (Spi1_Datar); Spi1 Polynomial Register (Spi1_Rcrcr); Spi1 Receive Crc Register (Spi1_Tcrcr) - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual
2 CHSID
1 TXE
0 RXNE

14.3.4 SPI Status register (SPI1_DATAR)

Offset address: 0x0C
15 14 13 12
Bit Name
[15:0] DR

14.3.5 SPI1 Polynomial register (SPI1_RCRCR)

Offset address: 0x10
15 14 13 12
Bit Name
[15:0] CRCPOLY

14.3.6 SPI1 Receive CRC register (SPI1_TCRCR)

Offset address: 0x18
15 14 13 12
Bit Name
[15:0] RXCRC
V1.3
Channel side. This flag is set by hardware and
reset by a software sequence.
1：Channel Right has to be transmitted or has
RO
been received.
0：Channel Left has to be transmitted or has been
received.
Transmit buffer empty.
1：Tx buffer empty.
RO
0：Tx buffer not empty.
Receive buffer not empty.
RO 1：Rx buffer not empty.
0：Rx buffer empty.
11 10 9 8
DR
Access
Data register. The data registers are used to store
the received data or pre-store the data to be sent
out, so the reading and writing of the data registers
actually correspond to the operation of different
areas, where the read pairs use the receive buffer
and the write pairs correspond to the send buffer.
RW Data can be received and sent in 8 or 16 bits, and
it is necessary to determine how many bits of data
to use before transmission. When using 8 bits for
data transmission, only the lower 8 bits of the data
registers are used, and the higher 8 bits are forced
to 0 for reception. using a 16-bit data structure
causes all 16 bits of the data registers to be used.
11 10 9 8
CRCPOLY[15:0]
Access
CRC polynomial.
RW
polynomial for the CRC calculation.
11 10 9 8
RXCRC
Access
RO Rx CRC. Store the result of the calculated CRC
7 6 5
Description
7 6 5
Description
This register contains the
7 6 5
Description
163
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0
1
0
4 3 2 1
Reset value
0
4 3 2 1
Reset value
7
4 3 2 1
Reset value
0
0
0
0