Compare/Capture Control Register 2 (Tim2_Chctlr2) - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual
[11:10] IC2PSC
[9:8] CC2S
[7:4] IC1F
[3:2] IC1PSC
[1:0] CC1S

11.4.8 Compare/Capture Control Register 2 (TIM2_CHCTLR2)

Offset address: 0x1C
The channel can be used in input (capture mode) or output (compare mode), and the direction of the channel
is defined by the corresponding CCxS bit. The other bits of this register serve different purposes in input and
output modes. OCxx describes the function of the channel in output mode and ICxx describes the function of
the channel in input mode.
15 14 13 12
OC4CE OC4M[2:0]
IC4F[3:0]
Comparison mode (pin direction is output).
Bit Name
15 OC4CE
[14:12] OC4M
11 OC4PE
10 OC4FE
[9:8] CC4S
7 OC3CE
V1.3
1100: sampling frequency Fsampling = Fdts/16, N = 8.
0101: sampling frequency Fsampling = Fdts/2, N = 8.
1101: sampling frequency Fsampling = Fdts/32, N = 5.
0110: sampling frequency Fsampling = Fdts/4, N = 6.
1110: sampling frequency Fsampling = Fdts/32, N = 6.
0111: sampling frequency Fsampling = Fdts/4, N = 8.
1111: Sampling frequency Fsampling=Fdts/32, N=8.
Compare capture channel 2 prescaler configuration
field, these 2 bits define the prescaler coefficient for
compare capture channel 2. Once CC1E = 0, the
prescaler is reset.
RW 00: without prescaler, one capture is triggered for each
edge detected on the capture input.
01: capture triggered every 2 events.
10: capture triggered every 4 events.
11: Capture is triggered every 8 events.
Compare the capture channel 2 input selection field,
these 2 bits define the direction of the channel
(input/output), and the selection of the input pin.
00: Comparative capture channel 1 channel is
configured as an output.
01: Comparison capture channel 1 channel is
configured as an input and IC1 is mapped on TI1.
RW 10: Comparison capture channel 1 channel is
configured as an input and IC1 is mapped on TI2.
11: The compare capture channel 1 channel is
configured as an input and IC1 is mapped on TRC. This
mode works only when the internal trigger input is
selected (by the TS bit).
Note: CC1S is writable only when the channel is off
(CC1E is 0).
RW Input capture filter 1 configuration field.
Compare the capture channel 1 prescaler configuration
RW
field.
RW Compare capture channel 1 input selection fields.
11 10 9
OC4PE OC4FE
CC4S[1:0]
IC4PSC[1:0]
Access
RW Compare capture channel 4 clear enable bit.
RW Compare the capture channel 4 mode setting field.
RW Compare Capture Register 4 preload enable bit.
RW Compare capture channel 4 fast enable bit.
RW Compare capture channel 4 input selection fields.
RW Compare capture channel 3 clear enable bit.
8 7 6 5
OC3CE OC3M[2:0]
IC3F[3:0]
Description
129
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4 3 2 1
OC3PE OC3FE
CC3S[1:0]
IC3PSC[1:0]
Reset
value
0
0
0
0
0
0
0
0
0
0
0
0