WCH CH32V003 Series Reference Manual page 111

CH32V003 Reference Manual
Bit Name
[15:13] Reserved
[12:8] DBL
[7:5] Reserved
[4:0] DBA
10.4.20 DMA Control register (TIM1_DMACFGR)
Offset address: 0x4C
15 14 13 12
Bit Name
[15:0] DMAADR
V1.3
Access
RO Reserved
The length of the DMA continuous transmission, the
RW
actual value of which is the value of this field + 1.
RO Reserved
These bits define the offset of the DMA in continuous
RW mode from the address where control register 1 is
located.
11 10 9 8
DMAADR[15:0]
Access
RW The address of the DMA in continuous mode.
111
Description
7 6 5 4
Description
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Reset
value
0
0
0
0
3 2 1 0
Reset
value
0