Pfic Interrupt Activation Status Register 2 (Pfic_Iactr2); Pfic Interrupt Priority Configuration Register (Pfic_Ipriorx); Pfic System Control Register (Pfic_Sctlr) - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual
[3:2] IACTS2_3
[1:0] Reserved

6.5.2.20 PFIC interrupt activation status register 2 (PFIC_IACTR2)

Offset address: 0x304
31 30 29 28
15 14 13 12
Bit Name
[31:7] Reserved
[6:0] IACTS32_38
6.5.2.21 PFIC Interrupt Priority Configuration Register (PFIC_IPRIORx) (x=0-63)
Offset address: 0x400-0x4FF
The controller supports 256 interrupts (0-255), each using 8 bits to set the control priority.
31
IPRIOR63 PRIO_255
...
IPRIORx PRIO_(4x+3)
...
IPRIOR0 PRIO_3
Bit Name
[2047:2040] IP_255
... ...
[31:24] IP_3
[23:16] IP_2
[15:8] IP_1
[7:0] IP_0

6.5.2.22 PFIC System Control Register (PFIC_SCTLR)

Offset address: 0xD10
31 30 29 28
V1.3
2#-3# interrupt execution status.
RO 1: current number interruption in execution.
0: The current number interrupt is not executed.
RO Reserved
27 26 25
11 10 9
Reserved
Access
RO Reserved
32#-38# Interrupt execution status.
1: Current number interruption in execution.
RO
0: The current number interrupt is not
executed.
24 23
PRIO_254
... ...
PRIO_(4x+2)
... ...
PRIO_2
Access
RW Same as IP_0 description.
... ...
RW Same as IP_0 description.
RW Same as IP_0 description.
RW Same as IP_0 description.
Number 0 interrupt priority configuration.
[7:6:4]: priority control bits.
If no nesting is configured, no preemption
RW bits.
Bit7 is preempted if 2 levels of nesting are
configured.
[5:0]: reserved, fixed to 0, write invalid.
27 26 25
24 23 22 21
Reserved
8 7 6 5
Description
16 15
PRIO_253
...
PRIO_(4x+1)
...
PRIO_1
Description
24 23 22 21
45
http://wch.cn
0
0
20 19 18 17
4 3 2 1
IACTS [38:32]
Reset value
0
0
8 7
PRIO_252
...
PRIO_(4x)
...
PRIO_0
Reset value
0
...
0
0
0
0
20 19 18 17
16
0
0
16