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CH32V003 Reference Manual
10.4.14 Compare/Capture register 1 (TIM1_CH1CVR)
Offset address: 0x34
15
14
13
12
Bit
Name
[15:0]
CH1CVR
10.4.15 Compare/Capture register 2 (TIM1_CH2CVR)
Offset address: 0x38
15
14
13
12
Bit
Name
[15:0]
CH2CVR
10.4.16 Compare/Capture register 3 (TIM1_CH3CVR)
Offset address: 0x3C
15
14
13
12
Bit
Name
[15:0]
CH3CVR
10.4.17 Compare/Capture register 4 (TIM1_CH4CVR)
Offset address: 0x40
15
14
13
12
Bit
Name
[15:0]
CH4CVR
10.4.18 Brake and Deadband Register (TIM1_BDTR)
Offset address: 0x44
15
14
13
12
MOE AOE BKP BKE OSSR OSSI LOCK[1:0]
Bit
Name
15
MOE
V1.3
11
10
9
8
CH1CVR[15:0]
Access
RW Compare the value of capture register channel 1.
11
10
9
8
CH2CVR[15:0]
Access
RW Compare the value of capture register channel 2.
11
10
9
8
CH3CVR [15:0]
Access
RW Compare the value of capture register channel 3.
11
10
9
8
CH4CVR [15:0]
Access
RW Compare the value of capture register channel 4.
11
10
9
8
Access
Main output enable bit. Once the brake signal is active,
it will be cleared asynchronously.
RW
1: Allow OCx and OCxN to be set as outputs.
0: Disable the output of OCx and OCxN or force to idle
state.
109
7
6
5
4
Description
7
6
5
4
Description
7
6
5
4
Description
7
6
5
4
Description
7
6
5
4
DTG[7:0]
Description
http://wch.cn
3
2
1
0
Reset
value
0
3
2
1
0
Reset
value
0
3
2
1
0
Reset
value
0
3
2
1
0
Reset
value
0
3
2
1
0
Reset
value
0
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