Comparing Capture Channels - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual
2) External clock source mode 1.
3) External clock source mode 2.
4) Encoder mode.
All 4 clock source sources mentioned above can be selected by these 4 operations.
11.2.3.1 Internal clock source (CK_INT)
If the general-purpose timer is started when the SMS field is held at 000b, then it is the internal clock source
(CK_INT) that is selected as the clock. At this point CK_INT is CK_PSC.
11.2.3.2 External clock source mode1
When the SMS domain is set to 111b, external clock source mode 1 is enabled. When external clock source 1
is enabled, TRGI is selected as the source for CK_PSC. it is worth noting that the user also needs to select the
source for TRGI by configuring the TS domain. the TS domain can select the following types of pulses as
clock sources.
1) Internal trigger (ITRx, x is 0,1,2,3).
2) Comparison of the signal after capturing channel 1 through the edge detector (TI1F_ED).
3) Comparison of signals TI1FP1, TI2FP2 of the capture channel.
4) The signal ETRF from the external clock pin input.
11.2.3.3 External clock source mode2
Use external trigger mode 2 to count on every rising or falling edge of the external clock pin input. When the
ECE position is set, the external clock source mode 2 is used. when using the external clock source mode 2,
ETRF is selected as CK_PSC. the ETR pin becomes ETRP after passing through the optional inverter (ETP),
divider (ETPS), and then ETRF after passing through the filter (ETF).
With the ECE position bit and the SMS set to 111b, then it is equivalent to the TS selecting ETRF as the input.
11.2.3.4 Encoder mode
Setting the SMS to 001b, 010b, 011b will enable the encoder mode. Enabling encoder mode allows you to
select a specific level in TI1FP1 and TI2FP2 to signal the output with another jump edge as the signal. This
mode is used when an external encoder is used. Refer to Section 10.3.9 for specific functions.
11.2.4 Counters and peripherals
CK_PSC is input to the prescaler (PSC) for dividing. the PSC is 16-bit and the actual dividing factor is equal
to the value of R16_TIMx_PSC + 1. CK_PSC goes through the PSC and becomes CK_INT. changing the
value of R16_TIM1_PSC does not take effect in real time, but is updated to the PSC after an update event. the
update event includes a UG bit clear and reset.

11.2.5 Comparing capture channels

The core of the comparative capture channel, which is the core of the timer to achieve complex functions, is
the comparative capture register, supplemented by digital filtering, frequency division and inter-channel
multiplexing in the peripheral input section, and comparator and output control in the output section. The
structure block diagram of the compare capture channel is shown in Figure 11-3.
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