Dma Channel X Peripheral Address Register (Dma_Paddrx); Dma Channel X Memory Address Register (Dma_Maddrx) - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual
8.3.5 DMA Channel x peripheral address register (DMA_PADDRx)(x=1/2/3/4/5/6/7 )
Offset address: 0x10 + (x-1)*20 + (y-1)*0x400
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit Name
[31:0] PA
Note: This register can only be changed when EN=0 and cannot be written when EN=1.
8.3.6 DMA Channel x memory address register (DMA_MADDRx)(x=1/2/3/4/5/6/7 )
Offset address: 0x14 + (x-1)*20 + (y-1)*0x400
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit Name
[31:0] MA
Note: This register can only be changed when EN=0 and cannot be written when EN=1.
V1.3
PA[31:0]
Access
Peripheral base address, which serves as the source or
destination address for peripheral data transfer.
When PSIZE[1:0]='01' (16 bits), the module automatically
RW ignores bit0 and the operation address is automatically 2-
byte aligned; when PSIZE[1:0]='10' (32 bits), the module
automatically ignores bit[1:0] and the operation address is
automatically 4-byte aligned.
MA[31:0]
Access
The memory data address, which serves as the source or
destination address for data transfers.
When MSIZE[1:0]='01'
RW automatically ignores bit0, and the operation address is
automatically 2-byte aligned; when MSIZE[1:0]='10' (32
bits), the module automatically ignores bit[1:0], and the
operation address is automatically 4-byte aligned.
69
Description
Description
(16 bits), the
http://wch.cn
Reset
value
0
Reset
value
module
0