Adc Injected Sequence Register (Adc_Isqr); Adc Injected Data Register (Adc_Idatarx); Adc Regular Data Register (Adc_Rdatar) - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual
[19:15] SQ4
[14:10] SQ3
[9:5] SQ2
[4:0] SQ1

9.3.12 ADC Injected sequence register (ADC_ISQR)

Offset address: 0x38
31 30 29 28
15 14 13 12
JSQ4[0] JSQ3[4:0]
Bit Name
[31:22] Reserved
[21:20] JL
[19:15] JSQ4
[14:10] JSQ3
[9:5] JSQ2
[4:0] JSQ1
Note: Unlike the regular conversion sequence, if the length of ILEN[1:0] is less than 4, the sequence order of
conversion starts from (4 - ILEN).
9.3.13 ADC Injected data register (ADC_IDATARx) (x=1/2/3/4)
Offset address: 0x3C + (x-1)*4
31 30 29 28
15 14 13 12
Bit Name
[31:16] Reserved
[15:0] IDATA

9.3.14 ADC Regular data register (ADC_RDATAR)

Offset address: 0x4C
31 30 29 28
V1.3
The number of the 4th conversion channel in the rule
RW
sequence (0-9).
The number of the 3th conversion channel in the rule
RW
sequence (0-9).
The number of the 2th conversion channel in the rule
RW
sequence (0-9).
The number of the 1th conversion channel in the rule
RW
sequence (0-9).
27 26 25 24
Reserved
11 10 9 8
JSQ2[4:0]
Access
RO Reserved
Inject the number of channels to be converted in the
RW channel conversion sequence.
00-11: 1-4 conversions.
The number of the 4th conversion channel in the injection
RW
sequence (0-9).
The number of the 3th conversion channel in the injection
RW
sequence (0-9).
The number of the 2th conversion channel in the injection
RW
sequence (0-9).
The number of the 1th conversion channel in the injection
RW
sequence (0-9).
27 26 25 24
Reserved
11 10 9 8
IDATA[15:0]
Access
RO Reserved
Injection of channel conversion data (data left- aligned or
RO
right-aligned).
27 26 25 24
DATA[31:16]
23 22 21
JL[1:0]
7 6 5
Description
23 22 21
7 6 5
Description
23 22 21
84
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20 19 18 17
JSQ4[4:1]
4 3 2 1
JSQ1[4:0]
Reset
value
20 19 18 17
4 3 2 1
Reset
value
20 19 18 17
0
0
0
0
16
0
0
0
0
0
0
0
16
0
0
0
16