Adc Control Register 2 (Adc_Ctlr2) - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual
9 AWDSGL
8 SCAN
7 JEOCIE
6 AWDIE
5 EOCIE
[4:0] AWDCH

9.3.3 ADC Control register 2 (ADC_CTLR2)

Offset address: 0x08
31 30 29 28
15 14 13 12
JEXT
JEXTSEL[2:0]
TRIG
Bit Name
[31:23] Reserved
22 SWSTART
21 JSWSTART
V1.3
Note: This mode requires disabling the external trigger
function of the injection channel.
In scan mode, use the analog watchdog enable bit on a
single channel.
RW 1: Using an analog watchdog on a single channel
(AWDCH[4:0] selection).
0: Use analog watchdog on all channels.
Scan mode enable bit.
1: Enables scan mode (continuous conversion of
RW
all channels selected by ADC_IOFRx and ADC_RSQRx).
0: Turn off the scan mode.
Inject the channel group end-of-conversion interrupt
enable bit.
1: Enables the injection of the channel group conversion
RW
completion interrupt (IEOC JEOC flag).
0: Turn off the injection channel group conversion
completion interrupt.
Analog watchdog interrupt enable bit.
1: Enabling the analog watchdog interrupt.
RW 0: Turn off the analog watchdog interrupt.
NOTE: In scan mode, this interrupt will abort the scan if it
occurs.
End of conversion (rule or injection channel group)
interrupt enable bit.
RW
1: Enables the end-of-conversion interrupt (EOC flag).
0: Turn off the end-of-conversion interrupt.
Analog watchdog channel selection bits.
00000: analog input channel 0.
RW 00001: Analog input channel 1.
...
01111: Analog input channel 15.
27 26 25
Reserved
11 10 9
ALIG
Reserved DMA
N
Access
RO Reserved
To start a rule channel conversion, you need to set the
software trigger to.
1: Initiate rule channel conversion.
RW
0: Reset state.
This bit is set by software and cleared to 0 by hardware
when conversion starts.
To initiate an injection channel transition, set the software
trigger to.
RW 1: Initiate injection channel conversion.
0: Reset state.
This bit is set by software and cleared to 0 by hardware or
24 23 22 21
SW JSW
STAR STAR
T T
8 7 6 5
Reserved
Description
79
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20 19 18 17
EXT
EXTSEL[2:0]
TRIG
4 3 2 1
RST CON
CAL
CAL T
0
0
0
0
0
0
16
Reser
ved
0
ADO
N
Reset
value
0
0
0