Table Of Contents - WCH CH32V003 Series Reference Manual

Table of Contents

Overview1
Memory And Bus Architecture2
Memory Image4
Memory Allocation5
Power Control (Pwr)6
Power Management6
Power-On Reset And Power-Down Reset6
Programmable Voltage Detector6
Low-Power Modes7
Low-Power Configuration Options8
Sleep Mode8
Standby Mode8
Auto-Wakeup (Awu)8
Register Description9
Power Control Register (Pwr_Ctlr)9
Power Control/Status Register (Pwr_Csr)9
Auto-Wakeup Control/Status Register (Pwr_Awucsr)10
Auto-Wakeup Window Comparison Value Register (Pwr_ Awuwr)10
Reset And Clock Control (Rcc)12
Power Reset12
System Reset12
System Clock Structure14
High-Speed Clock (Hsi/Hse)15
Low-Speed Clock (Lsi)16
Pll Clock16
Bus/Peripheral Clock16
Independent Watchdog Clock16
Clock Security System17
Clock Control Register (Rcc_Ctlr)17
Microcontroller Clock Output (Mco)17
Rcc-Related Registers List17
Clock Configuration Register0 (Rcc_Cfgr0)19
Clock Interrupt Register (Rcc_Intr)20
Apb2 Peripheral Reset Register (Rcc_Apb2Prstr)21
Apb1 Peripheral Reset Register22
Ahb Peripheral Clock Enable Register22
Apb2 Peripheral Clock Enable Register23
Apb1 Peripheral Clock Enable Register24
Control/Status Register24
Independent Watchdog (Iwdg)26
Enable Independent Watchdog26
Watchdog Configuration26
Control Register (Iwdg_Ctlr)27
Debug Mode27
Prescaler Register27
Reload Register28
Status Register28
Window Watchdog (Wwdg)29
Enable Window Watchdog29
Watchdog Reset30
Wake Up In Advance30
Wwdg-Related Registers List31
Control Register (Wwdg_Ctlr)31
Configuration Register (Wwdg_Cfgr)31
Status Register (Wwdg_Statr)32
Interrupt And Events (Pfic)33
Pfic Controller33
System Timer33
Vector Table Of Interrupts And Exceptions33
External Interrupt And Event Controller (Exti)34
Wake-Up Event34
External Interrupt (Exti) Interface Block Diagram34
External Event Mapping35
Exti Registers35
Exti Interrupt Mapping35
Interrupt Enable Register (Exti_Intenr)36
Event Enable Register (Exti_Evenr)36
Rising Edge Trigger Enable Register (Exti_Rtenr)36
Falling Edge Trigger Enable Register (Exti_Ftenr)36
Pfic Registers37
Software Interrupt Event Register (Exti_Swievr)37
Interrupt Flag Register (Exti_Intfr)37
Pfic Interrupt Enable Status Register 138
Pfic Interrupt Enable Status Register 239
Pfic Interrupt Pending Status Register 139
Pfic Interrupt Pending Status Register 240
Pfic Interrupt Priority Threshold Configuration Register40
Pfic Interrupt Configuration Register (Pfic_Cfgr)40
Pfic Interrupt Global Status Register (Pfic_Gisr)41
Pfic Vtf Interrupt Id Configuration Register (Pfic_Vtfidr)41
Pfic Vtf Interrupt 0 Address Register (Pfic_Vtfaddrr0)41
Pfic Vtf Interrupt 1 Address Register (Pfic_Vtfaddrr1)42
Pfic Interrupt Enable Setting Register 1 (Pfic_Ienr1)42
Pfic Interrupt Enable Setting Register 2 (Pfic_Ienr2)42
Pfic Interrupt Enable Clear Register 1 (Pfic_Irer1)43
Pfic Interrupt Enable Clear Register 2 (Pfic_Irer2)43
Pfic Interrupt Pending Setup Register 1 (Pfic_Ipsr1)43
Pfic Interrupt Pending Setup Register 2 (Pfic_Ipsr2)44
Pfic Interrupt Pending Clear Register 1 (Pfic_Ipsr1)44
Pfic Interrupt Pending Clear Register 2 (Pfic_Ipsr2)45
Pfic Interrupt Activation Status Register 1 (Pfic_Iactr1)45
Pfic Interrupt Activation Status Register 2 (Pfic_Iactr2)46
Pfic Interrupt Priority Configuration Register (Pfic_Ipriorx)46
Pfic System Control Register (Pfic_Sctlr)46
Dedicated Csr Registers47
Interrupt System Control Register (Intsyscr)47
Exception Entry Base Address Register (Mtvec)48
Stk Register Description48
System Count Control Register (Stk_Ctlr)48
System Count Status Register (Stk_Sr)49
System Counter Register (Stk_Cntl)49
Counting Comparison Register (Stk_Cmplr)50
Gpio And Alternate Function (Gpio/Afio)51
Gpio Module Basic Structure Block Diagram51
Gpio Initialization Function52
External Interrupts52
Multiplexing Functions52
Gpio Module Input Configuration Structure Block Diagram52
Gpio Module Output Configuration Structure Block Diagram53
Multiplexing Function Configuration53
Analog Input Configuration54
Gpio Settings For Peripherals54
Gpio Register Description55
Port Configuration Register Low (Gpiox_Cfglr)56
Port Input Register (Gpiox_Indr)56
Port Output Register (Gpiox_Outdr) (X=A/C/D)57
Port Reset/Set Register (Gpiox_Bshr) (X=A/C/D)57
Port Reset Register (Gpiox_Bcr) (X=A/C/D)57
Afio Register Description58
Port Configuration Lock Register (Gpiox_Lckr) (X=A/C/D)58
Remap Register 1 (Afio_Pcfr1)58
External Interrupt Configuration Register 1 (Afio_Exticr)60
Direct Memory Access Control (Dma)62
Dma Channel Processing62
Arbitration Priority62
Dma Configuration62
Programmable Total Data Transfer Size/Data Bit Width/Alignment63
Circular Mode63
Dma Processing Status63
Dma Request Mapping64
Dma-Related Registers List65
Dma1 Request Image65
Dma1 Peripheral Mapping Table For Each Channel65
Dma Interrupt Status Register (Dma_Intfr)66
Dma Interrupt Flag Clear Register (Dma_Intfcr)66
Dma Channel X Configuration Register (Dma_Cfgrx)67
Dma Channel X Number Of Data Register (Dma_Cntrx)68
Dma Channel X Peripheral Address Register (Dma_Paddrx)69
Dma Channel X Memory Address Register (Dma_Maddrx)69
Analog-To-Digital Converter (Adc)70
Adc Module Block Diagram71
Adc Configuration71
Module Power-Up71
Sampling Clock71
Channel Configuration72
Calibration72
Programmable Sampling Time72
Data Alignment72
External Trigger Source73
Conversion Mode73
Single Single-Channel Conversion Mode74
Single Scan Mode Conversion74
Single Intermittent Mode Conversion75
Trigger Injection75
Auto-Injection75
Simulating A Watchdog76
Continuous Conversion76
Analog Watchdog Threshold Area76
Analog Watchdog Channel Selection76
Adc-Related Registers List77
Adc Status Register (Adc_Statr)77
Adc Control Register 1 (Adc_Ctlr1)78
Adc Control Register 2 (Adc_Ctlr2)79
Adc Sample Time Configuration Register 1 (Adc_Samptr1)81
Adc Sample Time Configuration Register 2 (Adc_Samptr2)81
Adc Injected Channel Data Offset Register X (Adc_Iofrx)81
Adc Watchdog High Threshold Register (Adc_Wdhtr)82
Adc Watchdog Low Threshold Register (Adc_Wdhtr)82
Adc Regular Sequence Register 1(Adc_Rsqr1)82
Adc Regular Sequence Register 2(Adc_Rsqr2)83
Adc Regular Sequence Register 3(Adc_Rsqr3)83
Adc Injected Sequence Register (Adc_Isqr)84
Adc Injected Data Register (Adc_Idatarx)84
Adc Regular Data Register (Adc_Rdatar)84
Adc Delayed Data Register (Adc_Dlyr)85
Advanced-Control Timer (Adtm)86
Block Diagram Of Advanced-Control Timer Structure87
Clock Input88
Internal Clock Source (Ck_Int)88
External Clock Source Mode1/288
Block Diagram Of Ck_Psc Source For Advanced-Control Timer88
Counters And Peripherals89
Comparing Capture Channels And Perimeters89
Encoder Mode89
Block Diagram Of The Structure Of The Comparison Capture Channel90
Functionality And Implementation91
Input Capture Mode91
Compare Output Modes91
Forced Output Mode92
Pwm Input Mode92
Pwm Output Mode92
Complementary Outputs And Dead Zones92
Brake Signal93
Single Pulse Mode93
Complementary Outputs And Deadband93
Generation Of Single Pulse94
Tim1-Related Registers List95
Timer Synchronization Mode95
Control Register 1 (Tim1_Ctlr1)95
Control Register 2 (Tim1_Ctlr2)97
Slave Mode Control Register (Tim1_Smcfgr)98
Dma/Interrupt Enable Register (Tim1_Dmaintenr)100
Interrupt Status Register (Tim1_Intfr)101
Event Generation Register (Tim1_Swevgr)102
Compare/Capture Control Register 1 (Tim1_Chctlr1)104
Compare/Capture Control Register 2 (Tim1_Chctlr2)106
Compare/Capture Enable Register 2 (Tim1_Ccer)107
Counter For Advanced-Control Timer (Tim1_Cnt)108
Counting Clock Prescaler (Tim1_Psc)108
Auto-Reload Value Register (Tim1_Atrlr)108
Repeat Count Value Register (Tim1_Rptcr)108
Compare/Capture Register109
Brake And Deadband Register109
Dma Control Register (Tim1_Dmacfgr)110
General-Purpose Timer (Gptm)112
Difference Between General-Purpose Timer And Advanced-Control Timer113
General Timer Ck_Psc Source Block Diagram113
Comparing Capture Channels114
Compare Output Mode116
Tim2-Related Registers List119
Control Register 1 (Tim2_Ctlr1)119
Control Register 2 (Tim2_Ctlr2)121
Slave Mode Control Register (Tim2_Smcfgr)122
Interrupt Status Register (Tim2_Intfr)125
Compare/Capture Control Register 1 (Tim2_Chctlr1)126
Compare/Capture Control Register 2 (Tim2_Chctlr2)129
Compare/Capture Enable Register (Tim2_Ccer)130
Counter For General-Purpose Timer (Tim2_Cnt)130
Counting Clock Prescaler (Tim2_Psc)131
Auto-Reload Value Register (Tim2_Atrlr)131
Compare/Capture Registers131
Dma Control Register (Tim2_Dmacfgr)132
Dma Address Register For Continuous Mode (Tim2_Dmaadr)132
Universal Synchronous Asynchronous Receiver Transmitter (Usart)133
Baud Rate Generator134
Synchronous Mode134
Single-Wire Half-Duplex Mode135
Smart Card135
Irda136
Dma136
Interruptions136
(Un)Occurrence Of Parity Error Diagram136
Usart-Related Registers List137
Usart Status Register (Usart_Statr)137
Usart Data Register (Usart_Datar)139
Usart Control Register 1 (Usart_Ctlr1)140
Usart Control Register 2 (Usart_Ctlr2)141
Usart Control Register 3 (Usart_Ctlr3)142
Usart Guard Time And Prescaler Register (Usart_Gpr)143
Inter-Integrated Circuit (I2C) Interface144
I2C Timing Diagram144
Master Mode145
Slave Mode146
Error Conditions147
Bus Error (Berr)/Acknowledge Failure (Af)147
Arbitration Lost (Arlo)147
Overrun/Underrun Error (Ovr)147
Clock Extension148
Smbus148
Transmission Using Dma149
Reception Using Dma149
Packet Error Checking150
I2C-Related Registers List150
I2C Control Register150
I2C Own Address Register152
I2C Data Register (I2C_Datar)153
I2C Status Register153
I2C Clock Register (I2C1_Ckcfgr)156
Serial Peripheral Interface (Spi)157
Spi Structure Block Diagram157
Spi Mode158
Simplex Mode159
Crc159
Errors160
Spi-Related Registers List160
Master Mode Fault (Modf)160
Spi Control Register 2 (Spi1_Ctlr2)161
Spi Status Register (Spi1_Statr)162
Spi Status Register (Spi1_Datar)163
Spi1 Polynomial Register (Spi1_Rcrcr)163
Spi1 Receive Crc Register (Spi1_Tcrcr)163
Spi1 Transmit Crc Register (Spi1_Tcrcr)164
Spi High-Speed Control Register (Spi1_Hscr)164
Electronic Signature (Esig)165
Esig-Related Registers List165
Flash Capacity Register (Esig_Flacap)165
Uid Register165
Flash Memory And User Option Bytes167
Flash Memory Organization167
Flash Memory Programming And Security167
Security - Prevent Illegal Access (Read, Write, Erase)167
Control Register (Flash_Actlr)168
Fpec Key Register (Flash_Keyr)168
Obkey Register (Flash_Obtkeyr)168
Configuration Register (Flash_ Ctlr)169
Address Register (Flash_ Addr)170
Select Word Register (Flash_Obr)171
Write Protect Register (Flash_Wpr)171
Flash Memory Operation Flow172
Unlocking The Flash Memory172
Extended Key Register (Flash_Modekeyr)172
Boot Key Register (Flash_Boot_Modekeyp)172
Main Memory Standard Programming173
Main Memory Standard Erase173
Flash Page Erase174
Flash Whole Chip Erase174
Fast Programming Mode Unlocking175
Main Memory Fast Programming175
Main Memory Fast Erase175
User-Selected Words176
User-Selected Word Unlocking177
User-Selected Word Programming177
User-Selected Word Erasure178
Unprotecting Reads178
Extended Configuration179
Configuring The Extended Control Register (Extend_Ctr)179
Debug Support (Dbg)181
Debug Mcu Configuration Register (Dbgmcu_Cr)181