WCH CH32V003 Series Reference Manual page 124

CH32V003 Reference Manual
Reserv TD Reserv CC4D
ed E ed
Bit Name
15 Reserved
14 TDE
13 Reserved
12 CC4DE
11 CC3DE
10 CC2DE
9 CC1DE
8 UDE
7 Reserved
6 TIE
5 Reserved
4 CC4IE
3 CC3IE
2 CC2IE
1 CC1IE
0 UIE
V1.3
CC3D CC2D CC1D
E E E E
Access
RO Reserved
Trigger the DMA request enable bit.
RW 1: Allowing DMA requests to be triggered.
0: Triggering of DMA requests is prohibited.
RO Reserved
Compare the DMA request enable bit of capture
channel 4.
1: Allows comparison of DMA requests for capture
RW
channel 4.
0: Disable comparison of DMA requests for capture
channel 4.
Compare the DMA request enable bit of capture
channel 3.
1: Allows comparison of DMA requests for capture
RW
channel 3.
0: Disable comparison of DMA requests for capture
channel 3.
Compare the DMA request enable bit of capture
channel 2.
1: allows comparison of DMA requests for capture
RW
channel 2.
0: Disable comparison of DMA requests for capture
channel 2.
Compare the DMA request enable bit of capture
channel 1.
1: allows comparison of DMA requests for capture
RW
channel 1.
0: Disable comparison of DMA requests for capture
channel 1.
Updated DMA request enable bit.
RW 1: DMA requests that allow updates.
0: DMA requests for updates are disabled.
RO Reserved
Trigger the interrupt enable bit.
RW 1: Enables triggering of interrupts.
0: Trigger interrupt is disabled.
RO Reserved
Compare capture channel 4 interrupt enable bit.
RW 1: Allows comparison of capture channel 4 interrupts.
0: Disable compare capture channel 4 interrupt.
Compare capture channel 3 interrupt enable bit.
RW 1: Allows comparison of capture channel 3 interrupts.
0: Disable compare capture channel 3 interrupt.
Compare capture channel 2 interrupt enable bit.
RW 1: allows comparison of capture channel 2 interrupts.
0: Disable compare capture channel 2 interrupt.
Compare capture channel 1 interrupt enable bit.
RW 1: allows comparison of capture channel 1 interrupts.
0: Disable compare capture channel 1 interrupt.
Update the interrupt enable bit.
RW 1: Allowing updates to be interrupted.
0: Disable update interruption.
UD Reserv TI Reserv
E ed E ed
Description
124
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CC4I CC3I CC2I CC1I
E E E E
Reset
value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
UI
E