Pfic Interrupt Global Status Register (Pfic_Gisr); Pfic Vtf Interrupt Id Configuration Register (Pfic_Vtfidr); Pfic Vtf Interrupt 0 Address Register (Pfic_Vtfaddrr0) - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual
[6:0] Reserved

6.5.2.7 PFIC interrupt global status register (PFIC_GISR)

Offset address: 0x4C
31 30 29 28
15 14 13 12
Reserved
Bit Name
[31:10] Reserved
9 GPENDSTA
8 GACTSTA
[7:0] NESTSTA

6.5.2.8 PFIC VTF interrupt ID configuration register (PFIC_VTFIDR)

Offset address: 0x50
31 30 29 28
15 14 13 12
VTFID1
Bit Name
[31:16] Reserved
[15:8] VTFID1
[7:0] VTFID0

6.5.2.9 PFIC VTF interrupt 0 address register (PFIC_VTFADDRR0)

Offset address: 0x60
31 30 29 28
15 14 13 12
V1.3
Writing 1 is valid, writing 0 is invalid.
Note: Same function as the PFIC_SCTLR register
SYSRESET bit.
RO Reserved
27 26 25 24
Reserved
11 10 9 8
GPE GAC
ND T
STA STA
Access
RO Reserved
Are there any interrupts currently on hold.
RO
1: Yes; 0: No.
Are there any interrupts currently being executed.
RO
1: Yes; 0: No.
Current interrupt nesting status, currently supports
a maximum of 2 levels of nesting and a maximum
hardware stack depth of 2 levels.
RO
0x03: Level 2 interrupt in progress.
0x01: Level 1 interrupt in progress.
Other: no interrupt occurred.
27 26 25 24
Reserved
11 10 9 8
Access
RO Reserved
Configure the interrupt number of
RW
interrupt 1.
Configure the interrupt number of VTF interrupt
RW
0.
27 26 25 24
ADDR0[31:16]
11 10 9 8
ADDR0[15:1]
23 22 21
7 6 5
NESTSTA[7:0]
Description
23 22 21
7 6 5
Description
23 22 21
7 6 5
40
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0
20 19 18 17
4 3 2 1
Reset value
0
0
0
0
20 19 18 17
4 3 2 1
VTFID0
Reset value
0
VTF
0
0
20 19 18 17
4 3 2 1
16
0
16
0
16
0
VTF0E
N