Master Mode - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual
Figure 13-2 shows the functional block diagram of the I2C module.
SDA
SCL
SMBA

13.3 Master mode

In master mode, the I2C module dominates the data transfer and outputs the clock signal, and the data transfer
starts with a start event and ends with an end event. The steps to use master mode communication are.
Setting the correct clock in control register 2 (R16_I2Cx_CTLR2) and clock control register
(R16_I2Cx_CKCFGR).
Setting the appropriate rising edge in the rising edge register (R16_I2Cx_RTR).
Setting the PE bit in the control register (R16_I2Cx_CTLR1) to start the peripheral.
Set the START bit in the control register (R16_I2Cx_CTLR1) to generate the start event. After setting the
START bit, the I2C module will automatically switch to the main mode, the MSL bit will be set and the start
event will be generated. After the start event is generated, the SB bit will be set and if the ITEVTEN bit (in
R16_I2Cx_CTLR2) is set, an interrupt will be generated. The status register 1 (R16_I2Cx_STAR1) should be
read at this time and the SB bit will be cleared automatically after writing from the address to the data register.
If the 10-bit address mode is used, then the write data register sends the header sequence (the header sequence
is 11110xx0b, where the xx bits are the top two bits of the 10-bit address). After sending the header sequence,
the ADD10 bit of the status register will be set, and if the ITEVTEN bit has been set, an interrupt will be
generated, at this time the R16_I2Cx_STAR1 register should be read and the ADD10 bit cleared after writing
the second address byte to the data register. Then write the data register to send the second address byte, after
sending the second address byte, the ADDR bit of the status register will be set, if the ITEVTEN bit is already
set, an interrupt will be generated, at this time the R16_I2Cx_STAR1 register should be read and then read the
R16_I2Cx_STAR2 register once to clear the ADDR bit; if the 7-bit address mode, then write data register to
send address byte, after sending address byte, ADDR bit of status register will be set, if ITEVTEN bit has been
set, then interrupt will be generated, at this time, R16_I2Cx_STAR1 register should be read and then
R16_I2Cx_STAR2 register should be read once to clear ADDR bit; in 7-bit address mode, the the first byte
V1.3
Noise Data
filter control
Clock
Noise
filter control
Clock control
Register (CKCFGR)
Control registers
(CTLR1&CTLR2)
Status registers
(STAR1&STAR2)
145
Data register
Data shift register
Comparator PEC calculation
Own address register
Dual address register
PEC register
Control
logic
Interrupts DMA requests & ACK
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