Transmission Using Dma; Reception Using Dma - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual
13.9 DMA
DMA can be used to send and receive bulk data. The ITBUFEN bit of the control register cannot be set when
using DMA.
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Transmission using DMA

DMA mode can be activated by setting the DMAEN bit of the CTLR2 register. As long as the TxE bit is set,
data will be loaded by DMA from the set memory into the data register of the I2C. The following settings are
required to allocate channels for I2C.
1) Set the I2Cx_DATAR register address to the DMA_PADDRx register and the memory address in the
DMA_MADDRx register so that after each TxE event, data will be sent from memory to the
I2Cx_DATAR register.
2) Set the required number of bytes to be transferred in the DMA_CNTRx register. This value will be
decremented after each TxE event.
3) Configure the channel priority using the PL[0:1] bits in the DMA_CFGRx register.
4) Set the DIR bit in the DMA_CFGRx register and depending on the application requirements can be
configured to issue an interrupt request when the entire transfer is half or fully completed.
5) Activate the channel by setting the EN bit on the DMA_CFGRx register.
When the number of data transfers set in the DMA controller has been completed, the DMA controller sends
an end of transfer EOT/ EOT_1 signal to the I2C interface. A DMA interrupt will be generated if the interrupt
is allowed.
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Reception using DMA

DMA receive mode can be performed after setting DMAEN in the CTLR2 register. When using DMA receive,
DMA transfers the data in the data register to the preset memory area. The following steps are required to
allocate channels for I2C.
1) Set the I2Cx_DATAR register address to the DMA_PADDRx register and the memory address in the
DMA_MADDRx register so that after each RxNE event, data will be written to memory from the
I2Cx_DATAR register.
2) Set the required number of bytes to be transferred in the DMA_CNTRx register. This value will be
decremented after each RxNE event.
3) Configure the channel priority with PL[0:1] in the DMA_CFGRx register.
4) The DIR bit in the DMA_CFGRx register is cleared, and depending on the application requirements, an
interrupt request can be set to be issued when the data transfer is half or fully completed.
5) Set the EN bit in the DMA_CFGRx register to activate the channel.
When the number of data transfers set in the DMA controller has been completed, the DMA controller sends
an end of transfer EOT/EOT_1 signal to the I2C interface. A DMA interrupt will be generated if the interrupt
is allowed.
V1.3
Figure 13-4 I2C Interrupt Request
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