Watchdog Reset; Wake Up In Advance - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual
a comparison with the current counter, the value is configured by user software and will not change. It is
used as the upper limit value of the window time.
3) Watchdog enable: WDG_CTLR register WDGA bit software set to 1, to turn on the watchdog function,
you can system reset.
4) Feed the dog: i.e., refresh the current counter value and configure the T[6:0] bit field of the
WWDG_CTLR register. This action needs to be executed within the periodic window time after the
watchdog function is turned on, otherwise a watchdog reset action will occur.
l
Dog feeding window time
As shown in Figure 5-2, the gray area is the monitoring window area of the window watchdog, whose upper
time t2 corresponds to the point in time when the current counter value reaches the window value W[6:0]; its
lower time t3 corresponds to the point in time when the current counter value reaches 0x3F. This area time
t2<t<t3 can be fed with a dog operation (write T[6:0]) to refresh the current counter value.
Max=0x7F
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Watchdog reset

1) When the value of T[6:0] counter changes from 0x40 to 0x3F due to no timely dog feeding operation, a
"window watchdog reset" will occur and a system reset will be generated. That is, the T6-bit is detected
as 0 by the hardware and a system reset will occur.
Note: The application can write T6-bit to 0 by software to achieve system Reset, which is equivalent to
software reset function.
2) When the counter refresh action is executed within the disallowed dog feeding time, i.e., the write T[6:0]
bit field is operated within t
be generated.
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Wake up in advance

To prevent the system Reset caused by not refreshing the counter in time, the watchdog module provides an
early wakeup interrupt (EWI) notification. When the counter self-decreases to 0x40, an early wake-up signal
is generated and the WEIF flag is set to 1. If the EWI bit is set, a window watchdog interrupt will be triggered
at the same time. At this time, there is 1 counter clock cycle (self-decrement to 0x3F) before the hardware
reset, and the application can perform the dog feeding operation instantly within this time.
V1.3
l Figure 5-2 Counting mode of Window Watchdog
Y[6:0]CNT Current value
W[6:0]
Window area
0x3F
t1
t2
Refresh not allowed
T6 bit
RESET
Refresh will be
reset within
the disallowed
refresh time
time, a "window watchdog reset" will occur and a system Reset will
≤t≤t
1 2
Timeout:T *4096*2 *(T[5:0]+1])
WDGTB
PCLK1
t3
Refresh allowed
The counter will
reset when CNT
value<0x40
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Time